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| author | Bill Traynor <wmat@riscv.org> | 2022-11-28 15:32:14 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-28 15:32:14 -0500 |
| commit | 194cb531f51f5a8352bff1d758b4a90f68748d95 (patch) | |
| tree | dcc6777d0e8188379fbc7a3a0dffa0d66726dbd6 | |
| parent | a5841f90fd905dcf2f226c234ce9e111e3b89e72 (diff) | |
| download | riscv-isa-manual-194cb531f51f5a8352bff1d758b4a90f68748d95.zip riscv-isa-manual-194cb531f51f5a8352bff1d758b4a90f68748d95.tar.gz riscv-isa-manual-194cb531f51f5a8352bff1d758b4a90f68748d95.tar.bz2 | |
Updates to match latex.
Updated backticks to be normal single quotes.
Updated figure to match latex.
Commented out figure title.
| -rw-r--r-- | src/images/wavedrom/ct-unconditional.adoc | 6 | ||||
| -rw-r--r-- | src/rv32.adoc | 12 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc index 3b0c598..4d91da8 100644 --- a/src/images/wavedrom/ct-unconditional.adoc +++ b/src/images/wavedrom/ct-unconditional.adoc @@ -7,9 +7,9 @@ {bits: 7, name: 'opcode', attr: 'JAL', type: 8}, {bits: 5, name: 'rd', attr: 'dest', type: 2}, {bits: 8, name: 'imm[19:12]', type: 3}, - {bits: 1, name: '[11]', type: 3, attr: 'offset'}, - {bits: 10, name: 'imm[10:1]', type: 3}, - {bits: 1, name: '[20]', type: 3}, + {bits: 1, name: '[11]', type: 3}, + {bits: 10, name: 'imm[10:1]', attr: 'offset[20:1], type: 3}, + {bits: 4, name: '[20]', type: 3}, ]} .... diff --git a/src/rv32.adoc b/src/rv32.adoc index 43fb822..9bc76f6 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -386,10 +386,10 @@ the lower 5 bits of register _rs2_. include::images/wavedrom/nop.adoc[] [[nop]] -.NOP instructions +//.NOP instructions The NOP instruction does not change any architecturally visible state, -except for advancing the `pc` and incrementing any applicable +except for advancing the 'pc' and incrementing any applicable performance counters. NOP is encoded as ADDI _x0, x0, 0_. [NOTE] @@ -431,8 +431,8 @@ J-immediate encodes a signed offset in multiples of 2 bytes. The offset is sign-extended and added to the address of the jump instruction to form the jump target address. Jumps can therefore target a ±1 MiB range. JAL stores the address of the instruction -following the jump (`pc`+4) into register _rd_. The standard software -calling convention uses `x1` as the return address register and `x5` as +following the jump ('pc'+4) into register _rd_. The standard software +calling convention uses 'x1' as the return address register and 'x5' as an alternate link register. [NOTE] @@ -446,11 +446,11 @@ than the regular link register. ==== Plain unconditional jumps (assembler pseudoinstruction J) are encoded as -a JAL with _rd_=`x0`. +a JAL with _rd_='x0'. include::images/wavedrom/ct-unconditional.adoc[] [[ct-unconditional]] -.The unconditional-jump instruction, JAL +//.The unconditional-jump instruction, JAL The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target address is obtained by adding the |