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authorEdward Forgacs <eddie.forgacs@gmail.com>2022-04-11 07:54:02 +0200
committerGitHub <noreply@github.com>2022-04-10 22:54:02 -0700
commit14e7d02b726bbe1735a3f2b6d57b0aafe7aaf002 (patch)
tree883cd91110b8b0673acb1f459eb9edcaf5da139b
parenta5889d97d0790632e9927c2c462ea7823c68f08f (diff)
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Fix typo: "instruction" -> "instructions" (#834)
-rw-r--r--src/c.tex2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/c.tex b/src/c.tex
index 6cc0cb1..9ffa2ce 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -634,7 +634,7 @@ by 8, to the base address in register {\em \rsoneprime}. It expands to {\tt fsd
RVC provides unconditional jump instructions and conditional branch
instructions. As with base RVI instructions, the offsets of all RVC
-control transfer instruction are in multiples of 2 bytes.
+control transfer instructions are in multiples of 2 bytes.
\begin{center}
\begin{tabular}{S@{}L@{}Y}