Trying to separate figure label from admonition.

Trying to separate figure label from admonition.

1 files changed, 7 insertions, 7 deletions

diff --git a/src/rv32.adoc b/src/rv32.adoc
index 7acb4f5..64bdb4f 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -177,24 +177,24 @@ bit 31 of the instruction to speed sign-extension circuitry.
 include::images/wavedrom/instruction_formats.adoc[]
 [[base_instr]]
 .RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction's immediate field as is usually done.
-
+ 
 
 [NOTE]
 ====
-_Decoding register specifiers is usually on the critical paths in
+Decoding register specifiers is usually on the critical paths in
 implementations, and so the instruction format was chosen to keep all
 register specifiers at the same position in all formats at the expense
 of having to move immediate bits across formats (a property shared with
-RISC-IV aka. SPUR cite:[spur-jsscc1989])._
+RISC-IV aka. SPUR cite:[spur-jsscc1989]).
 
-_In practice, most immediates are either small or require all XLEN bits.
+In practice, most immediates are either small or require all XLEN bits.
 We chose an asymmetric immediate split (12 bits in regular instructions
 plus a special load-upper-immediate instruction with 20 bits) to
-increase the opcode space available for regular instructions._
+increase the opcode space available for regular instructions.
 
-_Immediates are sign-extended because we did not observe a benefit to
+Immediates are sign-extended because we did not observe a benefit to
 using zero-extension for some immediates as in the MIPS ISA and wanted
-to keep the ISA as simple as possible._
+to keep the ISA as simple as possible.
 ====
 
 === Immediate Encoding Variants