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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2022-06-21 23:42:29 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2022-06-21 23:42:29 -0700 |
| commit | 0f88f521258269b10e3f6d5ca1e9aa6058551953 (patch) | |
| tree | 9ea30dabcd126eeadfedd2e4417e15ab34a002aa | |
| parent | de5baeb330f5e16e83301b888795277793cdd29a (diff) | |
| download | riscv-isa-manual-0f88f521258269b10e3f6d5ca1e9aa6058551953.zip riscv-isa-manual-0f88f521258269b10e3f6d5ca1e9aa6058551953.tar.gz riscv-isa-manual-0f88f521258269b10e3f6d5ca1e9aa6058551953.tar.bz2 | |
Confirm that real-time clock synchronization is a mandate, but also relay in commentary that this is only an "as if" architectural requirement.
| -rw-r--r-- | src/counters.tex | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/counters.tex b/src/counters.tex index 7425a49..48f8bda 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -149,7 +149,14 @@ should be evaluated relative to the requirements of the platform. \end{commentary} The real-time clocks of all harts in a single user application -should be synchronized to within one tick of the real-time clock. +must be synchronized to within one tick of the real-time clock. + +\begin{commentary} +As with other architectural mandates, it suffices to appear ``as if'' +harts are synchronized to within one tick of the real-time clock, +i.e., software is unable to observe that there is a greater delta +between the real-time clock values observed on two harts. +\end{commentary} The RDINSTRET pseudoinstruction reads the low XLEN bits of the {\tt instret} CSR, which counts the number of instructions retired by |