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| author | Bill Traynor <wmat@riscv.org> | 2023-03-14 15:30:27 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-03-14 15:30:27 -0400 |
| commit | 0c84a551024e6bc671e020a719306b4ff6f53ae4 (patch) | |
| tree | 29b3cae94f61859c79358fa96858318f4be6be3c | |
| parent | e1f63aae70f793a2582838806f865af6fb0db123 (diff) | |
| download | riscv-isa-manual-0c84a551024e6bc671e020a719306b4ff6f53ae4.zip riscv-isa-manual-0c84a551024e6bc671e020a719306b4ff6f53ae4.tar.gz riscv-isa-manual-0c84a551024e6bc671e020a719306b4ff6f53ae4.tar.bz2 | |
Added senvcfg register diag
Added senvcfg register diag
| -rw-r--r-- | src/images/bytefield/senvcfg.edn | 34 | ||||
| -rw-r--r-- | src/supervisor.adoc | 8 |
2 files changed, 38 insertions, 4 deletions
diff --git a/src/images/bytefield/senvcfg.edn b/src/images/bytefield/senvcfg.edn new file mode 100644 index 0000000..6db866c --- /dev/null +++ b/src/images/bytefield/senvcfg.edn @@ -0,0 +1,34 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 16}]) +(def row-height 30 ) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 20) + +(draw-box "SXLEN-1" {:span 5 :text-anchor "start" :borders {}}) +(draw-box "8" {:span 5 :text-anchor "end" :borders {}}) +(draw-box "7" {:span 2 :borders {}}) +(draw-box "6" {:span 2 :borders {}}) +(draw-box "5" {:text-anchor "start" :borders {}}) +(draw-box "4" {:text-anchor "end" :borders {}}) +(draw-box "3" {:text-anchor "start" :borders {}}) +(draw-box "1" {:text-anchor "end" :borders {}}) +(draw-box "0" {:span 2 :borders {}}) + +(draw-box (text "WPRI" {:font-weight "bold"}) {:span 10}) +(draw-box "CBZE" {:span 2}) +(draw-box "CBCFE" {:span 2}) +(draw-box "CBIE" {:span 2}) +(draw-box (text "WPRI" {:font-weight "bold"}) {:span 2}) +(draw-box "FIOM" {:span 2}) + +(draw-box "SXLEN-8" {:span 10 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "3" {:span 2 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) + +----
\ No newline at end of file diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 98ffe07..ed8a832 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -506,12 +506,12 @@ of SXLEN and ILEN. ==== Supervisor Environment Configuration Register (`senvcfg`) The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as -shown in Figure #fig:senvcfg[[fig:senvcfg]], that controls certain +shown in <<senvcfg>>, that controls certain characteristics of the U-mode execution environment. -@Kcc@W@Wc & & & & & + -& & & & & + -SXLEN-8 & 1 & 1 & 2 & 3 & 1 + +[[senvcfg]] +.Supervisor environment configuration register (`senvcfg`). +include::images/bytefield/senvcfg.edn[] If bit FIOM (Fence of I/O implies Memory) is set to one in `senvcfg`, FENCE instructions executed in U-mode are modified so the requirement to |