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| author | Andrew Waterman <andrew@sifive.com> | 2024-02-27 17:12:40 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-27 17:12:40 -0800 |
| commit | 09c16b84dbb0b46ca7f3163d650bbcf7270b794f (patch) | |
| tree | 5958d7a713544a8e672fc8353653fb49c13fbdb7 | |
| parent | 36b5ce1e7480b44c407bbf08249ccd7018f713a3 (diff) | |
| parent | da025f60c7e1a824548432cf13b7a9f761542654 (diff) | |
| download | riscv-isa-manual-09c16b84dbb0b46ca7f3163d650bbcf7270b794f.zip riscv-isa-manual-09c16b84dbb0b46ca7f3163d650bbcf7270b794f.tar.gz riscv-isa-manual-09c16b84dbb0b46ca7f3163d650bbcf7270b794f.tar.bz2 | |
Merge pull request #1246 from riscv/clarify-sfence-w-inval
Clarify when SFENCE.W.INVAL/SFENCE.INVAL.IR are legal
| -rw-r--r-- | src/supervisor.adoc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 2b30893..e9f2855 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -2021,6 +2021,12 @@ or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual-instruction exception. When `hstatus`.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception. +Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode +raises an illegal-instruction exception. +Doing so in VU-mode raises a virtual-instruction exception. +SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the `mstatus`.TVM and +`hstatus`.VTVM fields and hence are always permitted in S-mode and VS-mode. + [NOTE] ==== SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be |