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| author | Bill Traynor <wmat@riscv.org> | 2024-04-29 17:52:06 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-29 14:52:06 -0700 |
| commit | 0965a03dd3d5ef5e55eac9a5ad9ea475d004659a (patch) | |
| tree | d94ccf4bf421b582a66829af11f249e1e455cef8 | |
| parent | c8773d5ad3b6d2b4bb92ed0c5ea26abac5b52c68 (diff) | |
| download | riscv-isa-manual-0965a03dd3d5ef5e55eac9a5ad9ea475d004659a.zip riscv-isa-manual-0965a03dd3d5ef5e55eac9a5ad9ea475d004659a.tar.gz riscv-isa-manual-0965a03dd3d5ef5e55eac9a5ad9ea475d004659a.tar.bz2 | |
Fixing italics issue. (#1371)riscv-isa-release-0965a03-2024-04-29
Fixes issue #1367 setting register name as monospaced in non-normative
text and italicizing and bolding the trailing variable.
| -rw-r--r-- | src/indirect-csr.adoc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/indirect-csr.adoc b/src/indirect-csr.adoc index 5c83b57..cb63a23 100644 --- a/src/indirect-csr.adoc +++ b/src/indirect-csr.adoc @@ -115,7 +115,7 @@ which the `miselect` value is allocated. [%unbreakable] [NOTE] ==== -Ordinarily, each_ `__mireg__i` _will access register state, access +Ordinarily, each `mireg`*_i_* will access register state, access read-only 0 state, or raise an illegal instruction exception. For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is recommended that the lower 32 bits of the register are accessed through one of `mireg`, `mireg2`, or `mireg3`, while the upper 32 bits are accessed through `mireg4`, `mireg5`, or `mireg6`, respectively. @@ -193,7 +193,7 @@ allocated. [%unbreakable] [NOTE] ==== -Ordinarily, each_ `__sireg__i` _will access register state, access +Ordinarily, each `sireg`*_i_* will access register state, access read-only 0 state, or, unless executing in a virtual machine (covered in the next section), raise an illegal instruction exception. ==== @@ -285,7 +285,7 @@ allocated. [%unbreakable] [NOTE] ==== -Ordinarily, each_ `__vsireg__i` _will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate. +Ordinarily, each `vsireg`*_i_* will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate. ==== Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always |