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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-16 19:56:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-09-16 19:56:01 -0700 |
| commit | 8f0dfec6e66ace3de708bd3ebb8905cb850a9d8f (patch) | |
| tree | 7e9f398f7e2b4694bd0131f843045aeae864e00f | |
| parent | 1ff8f5e3db057687425d9804fadba59ce722106a (diff) | |
| download | riscv-isa-manual-8f0dfec6e66ace3de708bd3ebb8905cb850a9d8f.zip riscv-isa-manual-8f0dfec6e66ace3de708bd3ebb8905cb850a9d8f.tar.gz riscv-isa-manual-8f0dfec6e66ace3de708bd3ebb8905cb850a9d8f.tar.bz2 | |
Tighten description of FCVTMOD assembly syntax
| -rw-r--r-- | src/zfa.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/zfa.tex b/src/zfa.tex index 41ae40c..cedc8b6 100644 --- a/src/zfa.tex +++ b/src/zfa.tex @@ -190,8 +190,8 @@ and the {\em rm} field set to 1 (RTZ). Other {\em rm} values are {\em reserved}. \begin{commentary} -The assembly syntax will require the RTZ rounding mode be explicitly -specified, i.e., {\tt fcvt.mod.w.d rd, rs1, rtz}. +The assembly syntax requires the RTZ rounding mode to be explicitly +specified, i.e., {\tt fcvtmod.w.d rd, rs1, rtz}. \end{commentary} \begin{commentary} |