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author | Andrew Waterman <andrew@sifive.com> | 2022-01-25 15:29:35 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-01-25 15:29:35 -0800 |
commit | 23a1255de3af5d5d6a7c6993dc9f44687446c6d4 (patch) | |
tree | 1b9919afb51da273ac08ffcc5fcd3a03006963ec | |
parent | 8fd6c3ada539bd92c71aac00d05556b9761e3940 (diff) | |
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Update priv preface to reflect draft status
-rw-r--r-- | src/priv-preface.tex | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 63d93e3..52adc14 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -11,6 +11,38 @@ ISA modules: \hline Module & Version & Status\\ \hline + \em Machine ISA & \em 1.13 & \em Draft \\ + \bf Supervisor ISA & \bf 1.12 & \bf Ratified \\ + \bf Svnapot Extension & \bf 1.0 & \bf Ratified \\ + \bf Svpbmt Extension & \bf 1.0 & \bf Ratified \\ + \bf Svinval Extension & \bf 1.0 & \bf Ratified \\ + \bf Hypervisor ISA & \bf 1.0 & \bf Ratified \\ + \hline + \end{tabular} +\end{table} +} + +The following compatible changes have been made to the Machine ISA since version 1.12: +\vspace{-0.2in} +\begin{itemize} + \parskip 0pt + \itemsep 1pt +\item Defined the {\tt misa}.V field to reflect that the V extension has been implemented. +\end{itemize} + +\section*{Preface to Version 20211203} + +This document describes the RISC-V privileged architecture. +This release, version 20211203, contains the following versions of the RISC-V +ISA modules: + +{ +\begin{table}[hbt] + \centering + \begin{tabular}{|c|l|c|} + \hline + Module & Version & Status\\ + \hline \bf Machine ISA & \bf 1.12 & \bf Ratified \\ \bf Supervisor ISA & \bf 1.12 & \bf Ratified \\ \bf Svnapot Extension & \bf 1.0 & \bf Ratified \\ |