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author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-19 19:05:40 +0900 |
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committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-20 10:04:40 +0900 |
commit | 11e9a8340a6ebd3c70fd1f5c5b69da049515dcfd (patch) | |
tree | 069be42b3a4353be609a84c1cca1b89806dac0a2 | |
parent | 0b1abc8e360652139158b5fca3b420b7e9d24aab (diff) | |
download | riscv-isa-manual-11e9a8340a6ebd3c70fd1f5c5b69da049515dcfd.zip riscv-isa-manual-11e9a8340a6ebd3c70fd1f5c5b69da049515dcfd.tar.gz riscv-isa-manual-11e9a8340a6ebd3c70fd1f5c5b69da049515dcfd.tar.bz2 |
Change compressed hint example
Because `C.ADD x0, t0` DOES encode the same hint as `ADD x0, x0, t0`
in Zihintntl extension (C.NTL.ALL and NTL.ALL), we need to change the
example (`C.ADD x0, a0 [x10]` and `ADD x0, x0, a0 [x10]` are chosen
considering simplicity and available space).
-rw-r--r-- | src/c.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1202,8 +1202,8 @@ instruction that happens not to mutate the architectural state. \end{commentary} RVC HINTs do not necessarily expand to their RVI HINT counterparts. For -example, \mbox{C.ADD {\em x0}, {\em t0}} might not encode the same HINT -as \mbox{ADD {\em x0}, {\em x0}, {\em t0}}. +example, \mbox{C.ADD {\em x0}, {\em a0}} might not encode the same HINT +as \mbox{ADD {\em x0}, {\em x0}, {\em a0}}. \begin{commentary} The primary reason to not require an RVC HINT to expand to an RVI HINT |