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| author | Andrew Waterman <andrew@sifive.com> | 2020-10-18 15:29:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-10-18 15:29:42 -0700 |
| commit | 48191f86c6e9a2c1bf57731e6f66fd9352591a11 (patch) | |
| tree | 5fae1863ca81d58497fe38d420fa6fd53c61698a | |
| parent | 03d49811ff1fefac28ebe7a19ecd31472997dfcd (diff) | |
| download | riscv-isa-manual-48191f86c6e9a2c1bf57731e6f66fd9352591a11.zip riscv-isa-manual-48191f86c6e9a2c1bf57731e6f66fd9352591a11.tar.gz riscv-isa-manual-48191f86c6e9a2c1bf57731e6f66fd9352591a11.tar.bz2 | |
Another attempt to clarify SEIP RMW semantics
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index cb9b26c..aa560f3 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1519,10 +1519,10 @@ external interrupt controller. When {\tt mip} is read with a CSR instruction, the value of the SEIP bit returned in the {\tt rd} destination register is the logical-OR of the software-writable bit and the -interrupt signal from the interrupt controller. -However, only the software-writeable SEIP bit participates in the -read-modify-write sequence of a CSRRS or CSRRC instruction; the signal -from the external interrupt controller does not participate. +interrupt signal from the interrupt controller, but the signal from the +interrupt controller is not used to calculate the value written to SEIP. +Only the software-writeable SEIP bit participates in the +read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} The SEIP field behavior is designed to allow a higher privilege |