From 48191f86c6e9a2c1bf57731e6f66fd9352591a11 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 18 Oct 2020 15:29:42 -0700 Subject: Another attempt to clarify SEIP RMW semantics --- src/machine.tex | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/machine.tex b/src/machine.tex index cb9b26c..aa560f3 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1519,10 +1519,10 @@ external interrupt controller. When {\tt mip} is read with a CSR instruction, the value of the SEIP bit returned in the {\tt rd} destination register is the logical-OR of the software-writable bit and the -interrupt signal from the interrupt controller. -However, only the software-writeable SEIP bit participates in the -read-modify-write sequence of a CSRRS or CSRRC instruction; the signal -from the external interrupt controller does not participate. +interrupt signal from the interrupt controller, but the signal from the +interrupt controller is not used to calculate the value written to SEIP. +Only the software-writeable SEIP bit participates in the +read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} The SEIP field behavior is designed to allow a higher privilege -- cgit v1.1