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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:14:58 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:14:58 -0800 |
| commit | 02e8477fb3570329f96c266463533b9c995d2fdd (patch) | |
| tree | 11e4618efdfe04e20a531e5ebe9062920ec46871 | |
| parent | 3995fe812e452d2aaa5d0b0aae6955eb80cc75c1 (diff) | |
| download | riscv-isa-manual-02e8477fb3570329f96c266463533b9c995d2fdd.zip riscv-isa-manual-02e8477fb3570329f96c266463533b9c995d2fdd.tar.gz riscv-isa-manual-02e8477fb3570329f96c266463533b9c995d2fdd.tar.bz2 | |
Clean up NMI/mepc wording
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index fe41b46..56f01b6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2584,8 +2584,8 @@ Non-maskable interrupts (NMIs) are only used for hardware error conditions, and cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart's interrupt enable bits. The {\tt mepc} register is written with the -address of the next instruction to be executed at the time the NMI was -taken, and {\tt mcause} is set to a value indicating the source of the +virtual address of the instruction that was interrupted, +and {\tt mcause} is set to a value indicating the source of the NMI. The NMI can thus overwrite state in an active machine-mode interrupt handler. |