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| author | Alex Bradbury <asb@asbradbury.org> | 2018-06-18 19:57:42 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-06-18 11:57:42 -0700 |
| commit | 1282cca4ef182ccceba6ae7144447f6b314ae17e (patch) | |
| tree | 33de62bd9b6f2eb81afdec17eb2ab52d4f8e1771 | |
| parent | 73257004b84fafe8433ec3df1938345618c68fbb (diff) | |
| download | riscv-isa-manual-1282cca4ef182ccceba6ae7144447f6b314ae17e.zip riscv-isa-manual-1282cca4ef182ccceba6ae7144447f6b314ae17e.tar.gz riscv-isa-manual-1282cca4ef182ccceba6ae7144447f6b314ae17e.tar.bz2 | |
Correct an instance of lr{w|d}.aq.rl to lr{w|d}.aqrl (#199)
| -rw-r--r-- | src/memory.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/memory.tex b/src/memory.tex index d0c71af..fad05ff 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -937,7 +937,7 @@ Power ISYNC maps on RISC-V to a FENCE.I followed by a FENCE~R,R; the latter fenc \hline Load-Exclusive & \tt lr.\{w|d\} \\ \hline - Load-Acquire-Exclusive & \tt lr.\{w|d\}.aq.rl \\ + Load-Acquire-Exclusive & \tt lr.\{w|d\}.aqrl \\ \hline Store & \tt s\{b|h|w|d\} \\ \hline |