From 1282cca4ef182ccceba6ae7144447f6b314ae17e Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@asbradbury.org>
Date: Mon, 18 Jun 2018 19:57:42 +0100
Subject: Correct an instance of lr{w|d}.aq.rl to lr{w|d}.aqrl (#199)

---
 src/memory.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/memory.tex b/src/memory.tex
index d0c71af..fad05ff 100644
--- a/src/memory.tex
+++ b/src/memory.tex
@@ -937,7 +937,7 @@ Power ISYNC maps on RISC-V to a FENCE.I followed by a FENCE~R,R; the latter fenc
     \hline
     Load-Exclusive            & \tt lr.\{w|d\}  \\
     \hline
-    Load-Acquire-Exclusive    & \tt lr.\{w|d\}.aq.rl \\
+    Load-Acquire-Exclusive    & \tt lr.\{w|d\}.aqrl \\
     \hline
     Store                     & \tt s\{b|h|w|d\}  \\
     \hline
-- 
cgit v1.1