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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-07 15:55:31 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-07 15:55:31 -0700 |
| commit | b124462c76b2de6e61a3a752701f422b223b7322 (patch) | |
| tree | 0f712e054ca17a9790dd83fbdbeddcb6be8ec50c | |
| parent | 06bddfbfa8b5479a4cceb62c2d6e3c3f9b6cdd4d (diff) | |
| download | riscv-isa-manual-b124462c76b2de6e61a3a752701f422b223b7322.zip riscv-isa-manual-b124462c76b2de6e61a3a752701f422b223b7322.tar.gz riscv-isa-manual-b124462c76b2de6e61a3a752701f422b223b7322.tar.bz2 | |
Remove SBI chapter
| -rw-r--r-- | src/priv-preface.tex | 2 | ||||
| -rw-r--r-- | src/riscv-privileged.tex | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index a2bdc94..047401d 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -63,6 +63,8 @@ architecture proposal. Changes from version 1.9.1 include: reserved and may be repurposed at a later date. \item A mechanism to improve virtualization performance by trapping S-mode virtual-memory management operations has been added. +\item The Supervisor Binary Interface (SBI) chapter has been removed, so + that it can be maintained as a separate specification. \end{itemize} \newpage diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index 9cca423..476eca2 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -77,7 +77,6 @@ Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, May 2017. \input{plic} \input{cfgstr} -\input{sbi} \input{priv-history} \bibliographystyle{plain} |