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author | Andrew Waterman <andrew@sifive.com> | 2017-05-07 15:50:39 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-05-07 15:50:39 -0700 |
commit | 9178feb31c5f7736ceb8023f37e17cbcab63a8cd (patch) | |
tree | 8a53410ac6479f4ceda79d4a2d50b4bbb33edc19 | |
parent | 137812654e54e5d765e21909679a2a24a38be123 (diff) | |
download | riscv-isa-manual-9178feb31c5f7736ceb8023f37e17cbcab63a8cd.zip riscv-isa-manual-9178feb31c5f7736ceb8023f37e17cbcab63a8cd.tar.gz riscv-isa-manual-9178feb31c5f7736ceb8023f37e17cbcab63a8cd.tar.bz2 |
Clarify compatibility note on priv spec cover
-rw-r--r-- | src/riscv-privileged.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index db10664..9cca423 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -15,8 +15,10 @@ Privileged Architecture Version \privrev \\ Document Version \privrev \\ {\bf Warning! This draft specification - will change before being accepted as standard by the RISC-V Foundation, so - implementations made to this draft specification will likely not conform + may change before being accepted as standard by the RISC-V Foundation. + While the editors intend future changes to this specification to be + forward compatible, it remains possible that + implementations made to this draft specification will not conform to the future standard.} \vspace{-0.1in}} |