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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-05 15:05:13 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-05 15:05:13 -0700 |
| commit | e2d41581a3b0d9ae78ae22287e723ec571a3c71a (patch) | |
| tree | 4a728ea65d3996fbfbcc50187b1bd1fc79fb8d54 | |
| parent | e6eb7fd1c29ad75bd51190b9e08fa11c9562063f (diff) | |
| parent | 2a0a7c44d9461fc764b1170a75c00c09f8eafa8d (diff) | |
| download | riscv-isa-manual-riscv-isa-release-e2d4158-2024-04-05.zip riscv-isa-manual-riscv-isa-release-e2d4158-2024-04-05.tar.gz riscv-isa-manual-riscv-isa-release-e2d4158-2024-04-05.tar.bz2 | |
Merge pull request #1311 from riscv/op-veriscv-isa-release-e6eb7fd-2024-04-05riscv-isa-release-e2d4158-2024-04-05
Opcode 0x77 is named OP-VE, for "Vector Extensions"
| -rw-r--r-- | src/rv-32-64g.adoc | 2 | ||||
| -rw-r--r-- | src/vector-crypto.adoc | 44 |
2 files changed, 23 insertions, 23 deletions
diff --git a/src/rv-32-64g.adoc b/src/rv-32-64g.adoc index 1818ddf..0464228 100644 --- a/src/rv-32-64g.adoc +++ b/src/rv-32-64g.adoc @@ -19,7 +19,7 @@ and RV64G. |00 |LOAD |LOAD-FP |_custom-0_ |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |48b |01 |STORE |STORE-FP |_custom-1_ |AMO |OP |LUI |OP-32 |64b |10 |MADD |MSUB |NMSUB |NMADD |OP-FP |OP-V |_custom-2/rv128_|48b -|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |_reserved_ |_custom-3/rv128_|≥80b +|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |OP-VE |_custom-3/rv128_|≥80b |=== <<opcodemap>> shows a map of the major opcodes for diff --git a/src/vector-crypto.adoc b/src/vector-crypto.adoc index 922195e..788575f 100644 --- a/src/vector-crypto.adoc +++ b/src/vector-crypto.adoc @@ -1199,7 +1199,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00001'}, @@ -1213,7 +1213,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00001'}, @@ -1300,7 +1300,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00000'}, @@ -1314,7 +1314,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00000'}, @@ -1406,7 +1406,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00011'}, @@ -1420,7 +1420,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00011'}, @@ -1511,7 +1511,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00010'}, @@ -1525,7 +1525,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00010'}, @@ -1616,7 +1616,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, @@ -1732,7 +1732,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, @@ -1845,7 +1845,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00111'}, @@ -2564,7 +2564,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, @@ -2692,7 +2692,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10001'}, @@ -3136,7 +3136,7 @@ Encoding (Vector-Vector) High part:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, @@ -3150,7 +3150,7 @@ Encoding (Vector-Vector) Low part:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, @@ -3348,7 +3348,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, @@ -3533,7 +3533,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, @@ -3726,7 +3726,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, @@ -3878,7 +3878,7 @@ Encoding:: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, @@ -4096,7 +4096,7 @@ Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10000'}, @@ -4110,7 +4110,7 @@ Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ -{bits: 7, name: 'OP-P'}, +{bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10000'}, @@ -4372,7 +4372,7 @@ Included in:: [[crypto_vector_instructions]] === Crypto Vector Cryptographic Instructions -OP-P (0x77) +OP-VE (0x77) Crypto Vector instructions except Zvbb and Zvbc // [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] |