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author | Kersten Richter <kersten@riscv.org> | 2024-05-03 19:30:00 -0500 |
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committer | GitHub <noreply@github.com> | 2024-05-03 17:30:00 -0700 |
commit | 87edab70ddd2fedc6d01603a65f393163025633f (patch) | |
tree | 5e4e9fd0d84fb6318312939c63d3906389892bd5 | |
parent | 0902ff22aeb2cabbd41f9b06a4af0523fd5ecfb1 (diff) | |
download | riscv-isa-manual-riscv-isa-release-87edab7-2024-05-04.zip riscv-isa-manual-riscv-isa-release-87edab7-2024-05-04.tar.gz riscv-isa-manual-riscv-isa-release-87edab7-2024-05-04.tar.bz2 |
Update supervisor.adoc (#1382)riscv-isa-release-87edab7-2024-05-04
https://github.com/riscv/riscv-isa-manual/issues/1370
Signed-off-by: Kersten Richter <kersten@riscv.org>
-rw-r--r-- | src/supervisor.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 6c2276d..5e33c4b 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -2186,14 +2186,14 @@ the trap handler commonly employs an `SRET` instruction to return from the trap. When Svvptc is implemented, the stores it executes to change the Valid bit of the PTEs from 0 to 1 then become visible to implicit references to those PTEs within a bounded timeframe. This visibility pertains to the instructions like -the one causing the page-fault or those accessing new memory regions. A +the one causing the page fault or those accessing new memory regions. A memory-management fence can be used to force immediate visibility of these PTE updates to all implicit references associated with instructions following the memory-management fence. However, when Svvptc is implemented, visibility (in a bounded amount of time) is guaranteed and use of a memory-management fence is not required in these scenarios. While this approach might lead to an occasional gratuitous page-fault, the performance benefit of omitting the memory-management -fence instructions outweighs the occasional cost of a gratuitous page-fault. +fence instructions outweighs the occasional cost of a gratuitous page fault. ==== //// |