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| author | Beeman Strong <97133824+bcstrongx@users.noreply.github.com> | 2024-08-06 14:56:59 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-06 21:56:59 +0000 |
| commit | 340d4b1c168bcf9fdff45593093263a1273b3e0e (patch) | |
| tree | 46fd29f68c00f965a2130fd0c4c434a398b06b27 | |
| parent | d2999932625d2cab25bb2081f7da915411e65ad3 (diff) | |
| download | riscv-isa-manual-riscv-isa-release-340d4b1-2024-08-06.zip riscv-isa-manual-riscv-isa-release-340d4b1-2024-08-06.tar.gz riscv-isa-manual-riscv-isa-release-340d4b1-2024-08-06.tar.bz2 | |
Update smcntrpmf.adoc (#1582)riscv-isa-release-340d4b1-2024-08-06
Remove claim that minstretcfg/mcyclecfg bits 57:56 are reserved for future priv modes
Signed-off-by: Beeman Strong <97133824+bcstrongx@users.noreply.github.com>
| -rw-r--r-- | src/smcntrpmf.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc index ca87901..c47402f 100644 --- a/src/smcntrpmf.adoc +++ b/src/smcntrpmf.adoc @@ -34,7 +34,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil When all __x__INH bits are zero, event counting is enabled in all modes. -For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. Bits 57:56 are reserved for possible future modes. +For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR. |