Isolate N extension into its own chapter in the priv specn-ext

9 files changed, 353 insertions, 369 deletions

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index 6df0ebc..6ac03a1 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -110,8 +110,8 @@ do so.
 Conversely, when V=0, the VS CSRs do not ordinarily affect the behavior of
 the machine other than being readable and writable by CSR instructions.
 
-A few standard supervisor CSRs ({\tt sedeleg}, {\tt sideleg},
-and {\tt scounteren}) have no matching VS CSR.
+A few standard supervisor CSRs ({\tt scounteren} and, if the N extension
+is implemented, {\tt sedeleg} and {\tt sideleg}) have no matching VS CSR.
 These supervisor CSRs continue to have their usual function and
 accessibility even when V=1, except with VS-mode and VU-mode substituting
 for HS-mode and U-mode.
@@ -341,13 +341,7 @@ HSXLEN \\
 The {\tt hedeleg} and {\tt hideleg} registers are only active when V=1.  When
 V=1, a trap that has been delegated to HS-mode (using {\tt medeleg} or {\tt
 mideleg}) is further delegated to VS-mode if the corresponding {\tt hedeleg} or
-{\tt hideleg} bit is set.  If the N extension for user-mode interrupts
-is implemented, the VS-mode guest may further delegate the interrupt
-to VU-mode by setting the corresponding bit in {\tt sedeleg} or {\tt sideleg}.
-
-When V=0 and the N extension for user-mode interrupts is implemented, a trap
-that has been delegated to HS-mode can be further delegated to U-mode by
-setting the corresponding bit in {\tt sedeleg} or {\tt sideleg}.
+{\tt hideleg} bit is set.
 
 When an access-fault or page-fault exception is caused by guest physical
 address translation, the trap is not delegated beyond HS-mode, regardless of
@@ -434,9 +428,9 @@ in HS-mode will raise an illegal instruction exception.
 \instbitrange{21}{0} \\
 \hline
 \multicolumn{1}{|c|}{MODE} &
-\multicolumn{1}{|c|}{0 (\warl)} &
-\multicolumn{1}{|c|}{VMID (\warl)} &
-\multicolumn{1}{|c|}{PPN  (\warl)} \\
+\multicolumn{1}{c|}{0 (\warl)} &
+\multicolumn{1}{c|}{VMID (\warl)} &
+\multicolumn{1}{c|}{PPN  (\warl)} \\
 \hline
 1 & 2 & 7 & 22 \\
 \end{tabular}
@@ -458,9 +452,9 @@ in HS-mode will raise an illegal instruction exception.
 \instbitrange{43}{0} \\
 \hline
 \multicolumn{1}{|c|}{MODE (\warl)} &
-\multicolumn{1}{|c|}{0 (\warl)} &
-\multicolumn{1}{|c|}{VMID (\warl)} &
-\multicolumn{1}{|c|}{PPN  (\warl)} \\
+\multicolumn{1}{c|}{0 (\warl)} &
+\multicolumn{1}{c|}{VMID (\warl)} &
+\multicolumn{1}{c|}{PPN  (\warl)} \\
 \hline
 4 & 2 & 14 & 44 \\
 \end{tabular}
@@ -570,7 +564,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \begin{center}
 \setlength{\tabcolsep}{4pt}
 \scalebox{0.95}{
-\begin{tabular}{cWcccccWcccccWcc}
+\begin{tabular}{cWcccccWccccWcc}
 \\
 \instbit{31} &
 \instbitrange{30}{20} &
@@ -584,8 +578,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \instbit{7} &
 \instbit{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
@@ -601,13 +594,11 @@ instructions that normally read or modify {\tt sstatus} actually access
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE}  &
-\multicolumn{1}{c|}{UIE}
-\\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
+1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}}
 \end{center}
 }
@@ -620,7 +611,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{cSFScccc}
+\begin{tabular}{cMFScccc}
 \\
 \instbit{VSXLEN-1} &
 \instbitrange{VSXLEN-2}{34} &
@@ -642,7 +633,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \hline
 1 & VSXLEN-35 & 2 & 12 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cccccccccccc}
+\begin{tabular}{cWWFccccWcc}
 \\
 &
 \instbitrange{16}{15} &
@@ -652,8 +643,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \instbit{7} &
 \instbit{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
@@ -665,12 +655,11 @@ instructions that normally read or modify {\tt sstatus} actually access
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
-\multicolumn{1}{c|}{UIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
- & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
+ & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -679,11 +668,6 @@ instructions that normally read or modify {\tt sstatus} actually access
 \label{vsstatusreg}
 \end{figure*}
 
-Fields UPIE and UIE of {\tt vsstatus} are aliases of the same fields in
-the HS-level {\tt sstatus}.
-The other fields of {\tt vsstatus} exist independently of HS-level
-{\tt sstatus}.
-
 The UXL field controls the effective XLEN for VU-mode, which may differ
 from the XLEN for VS-mode (VSXLEN).
 When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32.
@@ -732,10 +716,7 @@ in the {\tt hstatus} register is used to execute a load or store
 The {\tt vsip} register is a VSXLEN-bit read/write register that is
 VS-mode's version of supervisor register {\tt sip}, formatted as shown
 in Figure~\ref{vsipreg}.
-The {\tt vsip} register indicates pending VS-level and U-level
-interrupts.
-Fields UEIP, UTIP, and USIP are aliases of the same fields in the
-HS-level {\tt sip}.
+The {\tt vsip} register indicates pending VS-level interrupts.
 
 When V=1, {\tt vsip} substitutes for the usual {\tt sip}, so instructions
 that normally read or modify {\tt sip} actually access {\tt vsip}
@@ -755,28 +736,24 @@ for VS-level interrupts to reduce virtualization overhead.}
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{EccFccFcc}
+\begin{tabular}{KcFcFcc}
 \instbitrange{VSXLEN-1}{10} &
 \instbit{9} &
-\instbit{8} &
-\instbitrange{7}{6} &
+\instbitrange{8}{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
 \multicolumn{1}{|c|}{\wpri} &
 \multicolumn{1}{c|}{SEIP} &
-\multicolumn{1}{c|}{UEIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIP} &
-\multicolumn{1}{c|}{UTIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIP} &
-\multicolumn{1}{c|}{USIP} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-VSXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
+VSXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -788,10 +765,8 @@ VSXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
 The {\tt vsie} register is a VSXLEN-bit read/write register that is
 VS-mode's version of supervisor register {\tt sie}, formatted as shown in
 Figure~\ref{vsiereg}.
-The {\tt vsie} register contains interrupt enable bits for VS-level and
-U-level interrupts.
-Fields UEIE, UTIE, and USIE are aliases of the same fields in the
-HS-level {\tt sie}.
+The {\tt vsie} register contains interrupt enable bits for VS-level
+interrupts.
 
 When V=1, {\tt vsie} substitutes for the usual {\tt sie}, so instructions
 that normally read or modify {\tt sie} actually access {\tt vsie} instead.
@@ -802,28 +777,24 @@ the HS-level {\tt sie} register, not by {\tt vsie}.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{EccFccFcc}
+\begin{tabular}{KcFcFcc}
 \instbitrange{VSXLEN-1}{10} &
 \instbit{9} &
-\instbit{8} &
-\instbitrange{7}{6} &
+\instbitrange{8}{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
 \multicolumn{1}{|c|}{\wpri} &
 \multicolumn{1}{c|}{SEIE} &
-\multicolumn{1}{c|}{UEIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIE} &
-\multicolumn{1}{c|}{UTIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIE} &
-\multicolumn{1}{c|}{USIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-VSXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
+VSXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -1016,8 +987,8 @@ in the {\tt hstatus} register is used to execute a load or store
 \instbitrange{21}{0} \\
 \hline
 \multicolumn{1}{|c|}{MODE (\warl)} &
-\multicolumn{1}{|c|}{ASID (\warl)} &
-\multicolumn{1}{|c|}{PPN  (\warl)} \\
+\multicolumn{1}{c|}{ASID (\warl)} &
+\multicolumn{1}{c|}{PPN  (\warl)} \\
 \hline
 1 & 9 & 22 \\
 \end{tabular}
@@ -1037,8 +1008,8 @@ in the {\tt hstatus} register is used to execute a load or store
 \instbitrange{43}{0} \\
 \hline
 \multicolumn{1}{|c|}{MODE (\warl)} &
-\multicolumn{1}{|c|}{ASID (\warl)} &
-\multicolumn{1}{|c|}{PPN  (\warl)} \\
+\multicolumn{1}{c|}{ASID (\warl)} &
+\multicolumn{1}{c|}{PPN  (\warl)} \\
 \hline
 4 & 16 & 44 \\
 \end{tabular}
@@ -1258,11 +1229,11 @@ the hypervisor extension is provided and MXLEN=32.
 \multicolumn{1}{c|}{MPIE} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
-\multicolumn{1}{c|}{UIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
  & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \end{tabular}
@@ -1346,8 +1317,6 @@ MPV.  Table~\ref{h-mprv} enumerates the cases.
 
 The {\tt mstatus} register is a superset of the HS-level {\tt sstatus}
 register but is not a superset of {\tt vsstatus}.
-Because {\tt vsstatus} fields UPIE and UIE are aliased in the HS-level
-{\tt sstatus}, they are also aliased in {\tt mstatus}.
 
 \section{Two-Level Address Translation}
 \label{sec:two-level-translation}
@@ -1608,27 +1577,27 @@ calls from VS-mode use cause 10.  Table~\ref{hcauses} lists the
 possible M-mode and HS-mode exception codes when the hypervisor extension is
 present.
 
-\begin{table*}[h!]
+\begin{table*}[p]
 \begin{center}
 \begin{tabular}{|r|r|l|l|}
 
   \hline
   Interrupt & Exception Code  & Description \\
   \hline
-  1         & 0               & User software interrupt \\
+  1         & 0               & {\em Reserved} \\
   1         & 1               & Supervisor software interrupt \\
-  1         & 2               & {\em Reserved for future standard use} \\
+  1         & 2               & {\em Reserved} \\
   1         & 3               & Machine software interrupt \\ \hline
-  1         & 4               & User timer interrupt \\
+  1         & 4               & {\em Reserved} \\
   1         & 5               & Supervisor timer interrupt \\
-  1         & 6               & {\em Reserved for future standard use} \\
+  1         & 6               & {\em Reserved} \\
   1         & 7               & Machine timer interrupt \\ \hline
-  1         & 8               & User external interrupt \\
+  1         & 8               & {\em Reserved} \\
   1         & 9               & Supervisor external interrupt \\
-  1         & 10              & {\em Reserved for future standard use} \\
+  1         & 10              & {\em Reserved} \\
   1         & 11              & Machine external interrupt \\ \hline
-  1         & 12--15          & {\em Reserved for future standard use} \\
-  1         & $\ge$16         & {\em Reserved for platform use} \\ \hline
+  1         & 12--15          & {\em Reserved} \\
+  1         & $\ge$16         & {\em Available for platform use} \\ \hline
   0         & 0               & Instruction address misaligned \\
   0         & 1               & Instruction access fault \\
   0         & 2               & Illegal instruction \\
@@ -1643,13 +1612,13 @@ present.
   0         & 11              & Environment call from M-mode \\
   0         & 12              & Instruction page fault \\
   0         & 13              & Load page fault \\
-  0         & 14              & {\em Reserved for future standard use} \\
+  0         & 14              & {\em Reserved} \\
   0         & 15              & Store/AMO page fault \\
-  0         & 16--23          & {\em Reserved for future standard use} \\
-  0         & 24--31          & {\em Reserved for custom use} \\
-  0         & 32--47          & {\em Reserved for future standard use} \\
-  0         & 48--63          & {\em Reserved for custom use} \\
-  0         & $\ge$64         & {\em Reserved for future standard use} \\
+  0         & 16--23          & {\em Reserved} \\
+  0         & 24--31          & {\em Available for custom use} \\
+  0         & 32--47          & {\em Reserved} \\
+  0         & 48--63          & {\em Available for custom use} \\
+  0         & $\ge$64         & {\em Reserved} \\
   \hline
 \end{tabular}
 \end{center}
@@ -1664,16 +1633,10 @@ separately.
 
 When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless
 delegated by {\tt medeleg} or {\tt mideleg}, in which case it goes to HS-mode.
-If the N extension for user-mode interrupts is implemented, then U-mode
-traps destined for HS-mode may be further delegated to U-mode using the {\tt
-sedeleg} and {\tt sideleg} CSRs.
-
 When a trap occurs in VS-mode or VU-mode, it goes to M-mode, unless
 delegated by {\tt medeleg} or {\tt mideleg}, in which case it goes to HS-mode,
 unless further delegated by {\tt hedeleg} or {\tt hideleg}, in which case it
-goes to VS-mode.  If the N extension for user-mode interrupts is implemented,
-then VU-mode traps destined for VS-mode may be further delegated to VU-mode
-using the {\tt sedeleg} and {\tt sideleg} CSRs.
+goes to VS-mode.
 
 When a trap is taken into M-mode, virtualization mode V gets set to~0,
 and {\tt mstatus}.MPV and {\tt mstatus}.MPP are set according to
@@ -1735,6 +1698,9 @@ and the virtualization mode V remains~1.
 \label{h-vspp}
 \end{table*}
 
+
+\FloatBarrier
+
 \section{Trap Return}
 
 The MRET instruction is used to return from a trap taken into M-mode.
diff --git a/src/machine.tex b/src/machine.tex
index 6adf4f3..271087d 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -361,14 +361,14 @@ The {\tt mstatus} register is an MXLEN-bit read/write register
 formatted as shown in Figure~\ref{mstatusreg} for RV64 and
 Figure~\ref{mstatusreg-rv32} for RV32.  The {\tt mstatus}
 register keeps track of and controls the hart's current operating
-state.  Restricted views of the {\tt mstatus} register appear as the
-{\tt sstatus} and {\tt ustatus} registers in the S-level and U-level
-ISAs respectively.
+state.  A restricted view of {\tt mstatus} appears as the
+{\tt sstatus} register in the S-level ISA.
 
 \begin{figure*}[h!]
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
+\scalebox{0.95}{
 \begin{tabular}{cRccccYcccccc}
 \\
 \instbit{MXLEN-1} &
@@ -400,8 +400,9 @@ ISAs respectively.
  \\
 \hline
 1 & MXLEN-39 & 1 & 1 & 2 & 2 & 9 & 1 & 1 & 1 & 1 & 1 & \\
-\end{tabular}
-\begin{tabular}{ccccccccccccccc}
+\end{tabular}}
+\scalebox{0.95}{
+\begin{tabular}{ccWWcWccccccccc}
 \\
 &
 \instbit{17} &
@@ -429,14 +430,14 @@ ISAs respectively.
 \multicolumn{1}{c|}{MPIE} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
-\multicolumn{1}{c|}{UIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
  & 1 & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
-\end{tabular}
+\end{tabular}}
 \end{center}
 }
 \vspace{-0.1in}
@@ -472,7 +473,7 @@ ISAs respectively.
 \hline
 1 & 8 & 1 & 1 & 1 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cccccccccccccc}
+\begin{tabular}{cWWcWccccccccc}
 \\
 &
 \instbitrange{16}{15} &
@@ -498,11 +499,11 @@ ISAs respectively.
 \multicolumn{1}{c|}{MPIE} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
-\multicolumn{1}{c|}{UIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
  & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \end{tabular}
@@ -551,8 +552,9 @@ would be hardwired to zero.
 \subsubsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} register}
 \label{privstack}
 
-Global interrupt-enable bits, MIE, SIE, and UIE, are provided for each
-privilege mode.  These bits are primarily used to guarantee atomicity
+Global interrupt-enable bits, MIE and SIE, are provided for M-mode and
+S-mode respectively.
+These bits are primarily used to guarantee atomicity
 with respect to interrupt handlers in the current privilege mode.
 
 \begin{commentary}
@@ -564,11 +566,13 @@ instruction.
 When a hart is executing in privilege mode {\em x}, interrupts are
 globally enabled when {\em x}\,IE=1 and globally disabled when {\em
   x}\,IE=0.  Interrupts for lower-privilege modes, {\em w}$<${\em x},
-are always globally disabled regardless of the setting of the
-lower-privilege mode's global {\em w}\,IE bit.  Interrupts for
+are always globally disabled regardless of the setting of any global
+{\em w}\,IE bit for the lower-privilege mode.
+Interrupts for
 higher-privilege modes, {\em y}$>${\em x}, are always globally enabled
-regardless of the setting of the higher-privilege mode's global {\em
-  y}\,IE bit.  Higher-privilege-level code can use separate
+regardless of the setting of the global {\em y}\,IE bit for the
+higher-privilege mode.
+Higher-privilege-level code can use separate
 per-interrupt enable bits to disable selected higher-privilege-mode
 interrupts before ceding control to a lower-privilege mode.
 
@@ -579,12 +583,13 @@ interrupts before ceding control to a lower-privilege mode.
   interrupt, or reset as means to regain control of the hart.
 \end{commentary}
 
-To support nested traps, each privilege mode {\em x} has a two-level
+To support nested traps, each privilege mode {\em x} that can respond to
+interrupts has a two-level
 stack of interrupt-enable bits and privilege modes.  {\em x}\,PIE
 holds the value of the interrupt-enable bit active prior to the trap,
 and {\em x}\,PP holds the previous privilege mode.  The {\em x}\,PP
 fields can only hold privilege modes up to {\em x}, so MPP is
-two bits wide, SPP is one bit wide, and UPP is implicitly zero.  When
+two bits wide and SPP is one bit wide.  When
 a trap is taken from privilege mode {\em y} into privilege mode {\em
   x}, {\em x}\,PIE is set to the value of {\em x}\,IE; {\em x}\,IE is set to
 0; and {\em x}\,PP is set to {\em y}.
@@ -598,8 +603,8 @@ interrupted context, will save the privilege stack before re-enabling
 interrupts, so only one entry per stack is required.
 \end{commentary}
 
-The MRET, SRET, or URET instructions are used to return from
-traps in M-mode, S-mode, or U-mode respectively.  When
+An MRET or SRET instruction is used to return from
+a trap in M-mode or S-mode respectively.  When
 executing an {\em x}\,RET instruction, supposing {\em x}\,PP holds the
 value {\em y}, {\em x}\,IE is set to {\em x}\,PIE; the privilege mode
 is changed to {\em y}; {\em x}\,PIE is set to 1; and {\em x}\,PP is
@@ -617,20 +622,6 @@ If the machine provides only U and M modes, then only a single
 hardware storage bit is required to represent either 00 or 11 in MPP.
 \end{commentary}
 
-User-level interrupts are an optional extension and have been
-allocated the ISA extension letter N.
-If user-level interrupts are omitted, the
-UIE and UPIE bits are hardwired to zero.  For all other supported
-privilege modes {\em x}, the {\em x}\,IE and {\em x}\,PIE must not
-be hardwired.
-
-\begin{commentary}
-User-level interrupts are primarily intended to support secure
-embedded systems with only M-mode and U-mode present, but can also be
-supported in systems running Unix-like operating systems to support
-user-level trap handling.
-\end{commentary}
-
 \subsubsection{Base ISA Control in {\tt mstatus} Register}
 \label{xlen-control}
 
@@ -1208,26 +1199,14 @@ a lower privilege level.  The machine exception delegation register
 ({\tt medeleg}) and machine interrupt delegation register ({\tt
   mideleg}) are MXLEN-bit read/write registers.
 
-In systems with all three privilege modes (M/S/U), setting a bit in
-{\tt medeleg} or {\tt mideleg} will delegate the corresponding trap in
-S-mode or U-mode to the S-mode trap handler. If U-mode traps are
-supported, S-mode may in turn set corresponding bits in the {\tt
-  sedeleg} and {\tt sideleg} registers to delegate traps that occur in
-U-mode to the U-mode trap handler.
-In systems with S-mode, the {\tt medeleg} and {\tt mideleg} registers must
-exist, whereas the {\tt sedeleg} and {\tt sideleg} registers should only exist
-if the N extension for user-mode interrupts is also implemented.
-
-In systems with two privilege modes (M/U) and support for U-mode
-traps, setting a bit in {\tt medeleg} or {\tt mideleg} will
-delegate the corresponding trap in U-mode to the U-mode trap handler.
-In systems with only M-mode and U-mode, the {\tt medeleg} and {\tt mideleg}
-registers should only be implemented if the N extension for user-mode
-interrupts is implemented.
-
-In systems with only M-mode, or with both M-mode and U-mode but
-without U-mode trap support, the {\tt medeleg} and {\tt mideleg}
-registers should not exist.
+In systems with S-mode, the {\tt medeleg} and {\tt mideleg} registers
+must exist, and setting a bit in
+{\tt medeleg} or {\tt mideleg} will delegate the corresponding trap, when
+occurring in S-mode or U-mode, to the S-mode trap handler.
+In systems without S-mode, the {\tt medeleg} and {\tt mideleg} registers
+should not exist (unless the N extension for user-mode interrupts is
+implemented).
+
 \begin{commentary}
   In versions 1.9.1 and earlier , these registers existed but were
   hardwired to zero in M-mode only, or M/U without N systems.  There
@@ -1236,18 +1215,18 @@ registers should not exist.
 \end{commentary}
 
 
-When a trap is delegated to a less-privileged mode {\em x}, the
-{\em x}\,{\tt cause} register is written with the trap cause; the
-{\em x}\,{\tt epc} register is written with the virtual address of
+When a trap is delegated to S-mode, the
+{\tt scause} register is written with the trap cause; the
+{\tt sepc} register is written with the virtual address of
 the instruction that took the trap; the
-{\em x}\,{\tt tval} register is written with an
-exception-specific datum; the {\em x}\,PP field
+{\tt stval} register is written with an
+exception-specific datum; the SPP field
 of {\tt mstatus} is written with the active privilege mode at the time of
-the trap; the {\em x}\,PIE field of {\tt mstatus} is written with the
-value of the {\em x}\,IE field at the time of the trap; and
-the {\em x}\,IE field of {\tt mstatus} is cleared.  The {\tt mcause} and
-{\tt mepc} registers and the MPP and MPIE fields of {\tt mstatus} are
-not written.
+the trap; the SPIE field of {\tt mstatus} is written with the
+value of the SIE field at the time of the trap; and
+the SIE field of {\tt mstatus} is cleared.
+The {\tt mcause}, {\tt mepc}, and {\tt mtval} registers and the MPP and
+MPIE fields of {\tt mstatus} are not written.
 
 An implementation shall not hardwire any delegation bits to one, i.e.,
 any trap that can be delegated must support not being delegated.  An
@@ -1315,9 +1294,9 @@ MXLEN \\
 layout of bits matching those in the {\tt mip} register (i.e., STIP interrupt
 delegation control is located in bit 5).
 
-Some exceptions cannot occur at less privileged modes, and corresponding
-{\em x}\,{\tt edeleg} bits should be hardwired to zero.  In particular,
-{\tt medeleg}[11] and {\tt sedeleg}[11:9] are all hardwired to zero.
+For exceptions that cannot occur in less privileged modes, the corresponding
+{\tt medeleg} bits should be hardwired to zero.  In particular,
+{\tt medeleg}[11] is hardwired to zero.
 
 \subsection{Machine Interrupt Registers ({\tt mip} and {\tt mie})}
 
@@ -1325,8 +1304,8 @@ The {\tt mip} register is an MXLEN-bit read/write register containing
 information on pending interrupts, while {\tt mie} is the
 corresponding MXLEN-bit read/write register containing interrupt enable
 bits.  Only the bits corresponding to lower-privilege software
-interrupts (USIP, SSIP), timer interrupts (UTIP, STIP),
-and external interrupts (UEIP, SEIP) in {\tt mip}
+interrupts (SSIP), timer interrupts (STIP),
+and external interrupts (SEIP) in {\tt mip}
 are writable through this CSR address; the remaining bits are
 read-only.
 
@@ -1339,18 +1318,19 @@ read-only.
 \end{commentary}
 
 Restricted views of the {\tt mip} and {\tt mie} registers appear as
-the {\tt sip}/{\tt sie}, and {\tt uip}/{\tt uie} registers in 
-S-mode and U-mode respectively.  If an interrupt is delegated to
-privilege mode {\em x} by setting a bit in the {\tt mideleg} register,
-it becomes visible in the {\em x}\,{\tt ip} register and is maskable
-using the {\em x}\,{\tt ie} register.  Otherwise, the corresponding
-bits in {\em x}\,{\tt ip} and {\em x}\,{\tt ie} appear to be hardwired
+the {\tt sip} and {\tt sie} registers for supervisor level.
+If an interrupt is delegated to
+S-mode by setting a bit in the {\tt mideleg} register,
+it becomes visible in the {\tt sip} register and is maskable
+using the {\tt sie} register.  Otherwise, the corresponding
+bits in {\tt sip} and {\tt sie} appear to be hardwired
 to zero.
 
 \begin{figure*}[h!]
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
+\scalebox{0.95}{
 \begin{tabular}{Rcccccccccccc}
 \instbitrange{MXLEN-1}{12} &
 \instbit{11} &
@@ -1370,18 +1350,18 @@ to zero.
 \multicolumn{1}{c|}{MEIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SEIP} &
-\multicolumn{1}{c|}{UEIP} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MTIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIP} &
-\multicolumn{1}{c|}{UTIP} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MSIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIP} &
-\multicolumn{1}{c|}{USIP} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
 MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
-\end{tabular}
+\end{tabular}}
 \end{center}
 }
 \vspace{-0.1in}
@@ -1393,6 +1373,7 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
+\scalebox{0.95}{
 \begin{tabular}{Rcccccccccccc}
 \instbitrange{MXLEN-1}{12} &
 \instbit{11} &
@@ -1412,18 +1393,18 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \multicolumn{1}{c|}{MEIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SEIE} &
-\multicolumn{1}{c|}{UEIE} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MTIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIE} &
-\multicolumn{1}{c|}{UTIE} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MSIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIE} &
-\multicolumn{1}{c|}{USIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
 MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
-\end{tabular}
+\end{tabular}}
 \end{center}
 }
 \vspace{-0.1in}
@@ -1431,38 +1412,36 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \label{miereg}
 \end{figure*}
 
-The MTIP, STIP, UTIP bits correspond to timer interrupt-pending bits
-for machine, supervisor, and user timer interrupts, respectively.  The
+The MTIP and STIP bits correspond to timer interrupt-pending bits
+for machine and supervisor timer interrupts, respectively.  The
 MTIP bit is read-only and is cleared by writing to the memory-mapped
-machine-mode timer compare register.  The UTIP and STIP bits may be
-written by M-mode software to deliver timer interrupts to lower
-privilege levels.  User and supervisor software may clear the UTIP and
-STIP bits with calls to the AEE and SEE respectively.
-
-There is a separate timer interrupt-enable bit, named MTIE, STIE, and
-UTIE for M-mode, S-mode, and U-mode timer interrupts respectively.
-
-Each lower privilege level has a separate software interrupt-pending
-bit (SSIP, USIP), which can be both read and written by CSR accesses
-from code running on the local hart at the associated or any higher
-privilege level. The machine-level MSIP bits are written by accesses
+machine-mode timer compare register.  The STIP bit may be
+written by M-mode software to deliver timer interrupts to S-mode.
+Supervisor software may clear the STIP bit with a call to the SEE.
+
+There is a separate timer interrupt-enable bit, named MTIE and STIE,
+for M-mode and S-mode timer interrupts respectively.
+
+Supervisor level has a software interrupt-pending
+bit (SSIP), which can be both read and written by CSR accesses
+from code running on the local hart in S-mode or M-mode.
+The machine-level MSIP bit is written by accesses
 to memory-mapped control registers, which are used by remote harts to
 provide machine-mode interprocessor interrupts.  Interprocessor
-interrupts for lower privilege levels are implemented through
-implementation-specific mechanisms, e.g., via calls to an AEE or SEE,
+interrupts at supervisor level are implemented through
+implementation-specific mechanisms, e.g., via calls to an SEE,
 which might ultimately result in
 a machine-mode write to the receiving hart's MSIP bit.  A hart can write its
 own MSIP bit using the same memory-mapped control register.
 
-The MSIE, SSIE, and USIE fields in the {\tt mie} CSR enable M-mode software
-interrupts, S-mode software interrupts, and U-mode software interrupts,
-respectively.
+The MSIE and SSIE fields in the {\tt mie} CSR enable M-mode software
+interrupts and S-mode software interrupts, respectively.
 
 \begin{commentary}
-We only allow a hart to directly write its own SSIP or USIP
-bits when running in the appropriate mode, as other harts might be
+We allow a hart to directly write only its own SSIP bit, not those of other
+harts, as other harts might be
 virtualized and possibly descheduled by higher privilege levels.  We
-rely on calls to the AEE and SEE to provide interprocessor interrupts
+rely on calls to the SEE to provide interprocessor interrupts
 for this reason.  Machine-mode harts are not virtualized and can
 directly interrupt other harts by setting their MSIP bits, typically
 using uncached I/O writes to memory-mapped control registers depending
@@ -1495,13 +1474,8 @@ from the external interrupt controller.
   slightly modified from regular CSR accesses as a result.
 \end{commentary}
 
-The UEIP field in {\tt mip} provides user-mode external interrupts when the
-N extension for user-mode interrupts is implemented.  It is defined
-analogously to SEIP.
-
-The MEIE, SEIE, and UEIE fields in the {\tt mie} CSR enable M-mode external
-interrupts, S-mode external interrupts, and U-mode external interrupts,
-respectively.
+The MEIE and SEIE fields in the {\tt mie} CSR enable M-mode external
+interrupts and S-mode external interrupts, respectively.
 
 \begin{commentary}
 The non-maskable interrupt is not made visible via the {\tt mip}
@@ -1510,16 +1484,16 @@ trap handler.
 \end{commentary}
 
 For all the various interrupt types (software, timer, and external),
-if a privilege level is not supported, or if U-mode is supported but
-the N extension is not supported, then the associated pending and
+if a privilege level is not supported, then the associated pending and
 interrupt-enable bits are hardwired to zero in the {\tt mip} and {\tt
   mie} registers respectively.  Hence, these are all effectively
 \warl\ fields.
 
 Implementations may add additional platform-specific interrupt sources to bits
 16 and above of the {\tt mip} and {\tt mie} registers.  Some platforms may
-avail these interrupts for custom use.  The other unallocated interrupt
-sources (15--12, 10, 6, and 2) are reserved for future standard use.
+make custom use of these interrupts.  The other unallocated interrupt
+sources (0, 2, 4, 6, 8, 10, and 12--15) are reserved for other possible
+standardized uses.
 
 An interrupt {\em i} will be taken if bit {\em i} is set in both {\tt
   mip} and {\tt mie}, and if interrupts are globally enabled.  By
@@ -1528,14 +1502,14 @@ privilege mode is less than M, or if the current privilege mode is M
 and the MIE bit in the {\tt mstatus} register is set.  If bit {\em i}
 in {\tt mideleg} is set, however, interrupts are considered to be
 globally enabled if the hart's current privilege mode equals the
-delegated privilege mode (S or U) and that mode's interrupt enable
-bit (SIE or UIE in {\tt mstatus}) is set, or if the current
+delegated privilege mode and that mode's interrupt enable
+bit ({\em x}\,IE in {\tt mstatus} for mode~{\em x}) is set, or if the current
 privilege mode is less than the delegated privilege mode.
 
 Multiple simultaneous interrupts destined for different privilege modes are
 handled in decreasing order of destined privilege mode.  Multiple simultaneous
 interrupts destined for the same privilege mode are handled in the following
-decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI.
+decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI.
 Synchronous exceptions are of lower priority than all interrupts.
 
 \begin{commentary}
@@ -2042,20 +2016,20 @@ codes.
   \hline
   Interrupt & Exception Code  & Description \\
   \hline	 
-  1         & 0               & User software interrupt \\
+  1         & 0               & {\em Reserved} \\
   1         & 1               & Supervisor software interrupt \\
-  1         & 2               & {\em Reserved for future standard use} \\
+  1         & 2               & {\em Reserved} \\
   1         & 3               & Machine software interrupt \\ \hline
-  1         & 4               & User timer interrupt \\
+  1         & 4               & {\em Reserved} \\
   1         & 5               & Supervisor timer interrupt \\
-  1         & 6               & {\em Reserved for future standard use} \\
+  1         & 6               & {\em Reserved} \\
   1         & 7               & Machine timer interrupt \\ \hline
-  1         & 8               & User external interrupt \\
+  1         & 8               & {\em Reserved} \\
   1         & 9               & Supervisor external interrupt \\
-  1         & 10              & {\em Reserved for future standard use} \\
+  1         & 10              & {\em Reserved} \\
   1         & 11              & Machine external interrupt \\ \hline
-  1         & 12--15          & {\em Reserved for future standard use} \\
-  1         & $\ge$16         & {\em Reserved for platform use} \\ \hline
+  1         & 12--15          & {\em Reserved} \\
+  1         & $\ge$16         & {\em Available for platform use} \\ \hline
   0         & 0               & Instruction address misaligned \\
   0         & 1               & Instruction access fault \\
   0         & 2               & Illegal instruction \\   
@@ -2070,13 +2044,13 @@ codes.
   0         & 11              & Environment call from M-mode \\
   0         & 12              & Instruction page fault \\
   0         & 13              & Load page fault \\
-  0         & 14              & {\em Reserved for future standard use} \\
+  0         & 14              & {\em Reserved} \\
   0         & 15              & Store/AMO page fault \\
-  0         & 16--23          & {\em Reserved for future standard use} \\
-  0         & 24--31          & {\em Reserved for custom use} \\
-  0         & 32--47          & {\em Reserved for future standard use} \\
-  0         & 48--63          & {\em Reserved for custom use} \\
-  0         & $\ge$64         & {\em Reserved for future standard use} \\
+  0         & 16--23          & {\em Reserved} \\
+  0         & 24--31          & {\em Available for custom use} \\
+  0         & 32--47          & {\em Reserved} \\
+  0         & 48--63          & {\em Available for custom use} \\
+  0         & $\ge$64         & {\em Reserved} \\
   \hline
 
 \end{tabular}
@@ -2331,17 +2305,16 @@ minor opcode.
 \multicolumn{1}{c|}{opcode} \\
 \hline
 12 & 5 & 3 & 5 & 7 \\
-MRET/SRET/URET & 0 & PRIV & 0 & SYSTEM \\
+MRET/SRET & 0 & PRIV & 0 & SYSTEM \\
 \end{tabular}
 \end{center}
 
 To return after handling a trap, there are separate trap return
-instructions per privilege level: MRET, SRET, and URET.  MRET is
+instructions per privilege level, MRET and SRET.  MRET is
 always provided. SRET must be provided if supervisor mode is
 supported, and should raise an illegal instruction exception otherwise. SRET
 should also raise an illegal instruction exception when TSR=1 in {\tt mstatus},
-as described in Section~\ref{virt-control}. URET is only provided if user-mode
-traps are supported, and should raise an illegal instruction otherwise.
+as described in Section~\ref{virt-control}.
 An {\em x}\,RET instruction can be executed in privilege mode {\em x}
 or higher, where executing a lower-privilege {\em x}\,RET instruction
 will pop the relevant lower-privilege interrupt enable and privilege
@@ -2425,7 +2398,7 @@ handler, the idle loop will resume execution.
 
 The WFI instruction can also be executed when interrupts are disabled.  The
 operation of WFI must be unaffected by the global interrupt bits in {\tt
-mstatus} (MIE/SIE/UIE) and the delegation registers {\tt [m|s]ideleg}
+mstatus} (MIE and SIE) and the delegation register {\tt mideleg}
 (i.e., the hart must resume if a locally enabled interrupt becomes pending,
 even if it has been delegated to a less-privileged mode), but should honor the
 individual interrupt enables (e.g, MTIE) (i.e., implementations should
diff --git a/src/n.tex b/src/n.tex
index 00812a7..7185fc3 100644
--- a/src/n.tex
+++ b/src/n.tex
@@ -4,6 +4,12 @@
 \begin{commentary}
   This is a placeholder for a more complete writeup of the N
   extension, and to form a basis for discussion.
+
+  An ongoing topic of discussion is whether, for systems with only M and
+  U privilege modes, the N extension should be supplanted by S-mode without
+  virtual memory (i.e., with {\tt satp} hardwired to zero).
+  This approach would have similar hardware cost and would simplify the
+  architecture.
 \end{commentary}
 
 This chapter presents a proposal for adding RISC-V user-level
@@ -28,32 +34,13 @@ floating-point traps.
 
 \section{Additional CSRs}
 
-The user-visible CSRs added to support the N extension are listed in
-Table~\ref{tab:ncsrs}.
-
-\begin{table}[hbt]
-  \centering
-  \begin{tabular}{|l|l|l|}
-    \hline
-    Number   & Name           & Description \\
-    \hline
-    \tt 0x000 & \tt ustatus    & User status register. \\
-    \tt 0x004 & \tt uie        & User interrupt-enable register. \\
-    \tt 0x005 & \tt utvec      & User trap handler base address. \\
-    \tt 0x040 & \tt uscratch   & Scratch register for user trap handlers. \\
-    \tt 0x041 & \tt uepc       & User exception program counter. \\
-    \tt 0x042 & \tt ucause     & User trap cause. \\
-    \tt 0x043 & \tt utval      & User bad address or instruction. \\
-    \tt 0x044 & \tt uip        & User interrupt pending. \\
-    \hline
-  \end{tabular}
-  \caption{CSRs for N extension.}
-  \label{tab:ncsrs}
-\end{table}
-
-\section{User Status Register ({\tt ustatus})}
-
-The {\tt ustatus} register is an XLEN-bit read/write register
+New user-visible CSRs added to support the N extension.
+Their encodings are listed in Table~\ref{ucsrnames} in
+Chapter~\ref{chap:priv-csrs}.
+
+\subsection{User Status Register ({\tt ustatus})}
+
+The {\tt ustatus} register is a UXLEN-bit read/write register
 formatted as shown in Figure~\ref{ustatusreg}.  The {\tt ustatus}
 register keeps track of and controls the hart's current operating
 state.
@@ -63,7 +50,7 @@ state.
 \setlength{\tabcolsep}{4pt}
 \begin{tabular}{KccFc}
 \\
-\instbitrange{XLEN}{5} &
+\instbitrange{UXLEN}{5} &
 \instbit{4} &
 \instbitrange{3}{1} &
 \instbit{0} \\
@@ -73,7 +60,7 @@ state.
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UIE} \\
 \hline
-XLEN-5 & 1 & 3 & 1 \\
+UXLEN-5 & 1 & 3 & 1 \\
 \end{tabular}
 \end{center}
 \vspace{-0.1in}
@@ -86,6 +73,9 @@ clear. The value of UIE is copied into UPIE when a user-level trap is
 taken, and the value of UIE is set to zero to provide atomicity for
 the user-level trap handler.
 
+The UIE and UPIE bits are mirrored in the {\tt mstatus} and {\tt sstatus}
+registers in the same bit positions.
+
 \begin{commentary}
   There is no UPP bit to hold the previous privilege mode as it can
   only be user mode.
@@ -98,12 +88,132 @@ copies UPIE into UIE, then sets UPIE.
   and help catch coding errors.
 \end{commentary}
 
-\section{Other CSRs}
-The remaining CSRs function in an analogous way to the trap handling
-registers defined for M-mode and S-mode.
+\subsection{User Interrupt Registers ({\tt uip} and {\tt uie})}
+
+The {\tt uip} register is a UXLEN-bit read/write register containing
+information on pending interrupts, while {\tt uie} is the corresponding
+UXLEN-bit read/write register containing interrupt enable bits.
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{KcFcFc}
+\instbitrange{UXLEN-1}{9} &
+\instbit{8} &
+\instbitrange{7}{5} &
+\instbit{4} &
+\instbitrange{3}{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{c|}{UEIP} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UTIP} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{USIP} \\
+\hline
+UXLEN-9 & 1 & 3 & 1 & 3 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{User interrupt-pending register ({\tt uip}).}
+\label{uipreg}
+\end{figure*}
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{KcFcFc}
+\instbitrange{UXLEN-1}{9} &
+\instbit{8} &
+\instbitrange{7}{5} &
+\instbit{4} &
+\instbitrange{3}{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{c|}{UEIE} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UTIE} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{USIE} \\
+\hline
+UXLEN-9 & 1 & 3 & 1 & 3 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{User interrupt-enable register ({\tt uie}).}
+\label{uiereg}
+\end{figure*}
+
+Three types of interrupts are defined: software interrupts, timer interrupts,
+and external interrupts.  A user-level software interrupt is triggered
+on the current hart by writing 1 to its user software interrupt-pending
+(USIP) bit in the {\tt uip} register.  A pending user-level software
+interrupt can be cleared by writing 0 to the USIP bit in {\tt uip}.
+User-level software interrupts are disabled when the USIE bit in the
+{\tt uie} register is clear.
+
+The ABI should provide a mechanism to send interprocessor interrupts to other
+harts, which will ultimately cause the USIP bit to be set in the recipient
+hart's {\tt uip} register.
+
+All bits besides USIP in the {\tt uip} register are read-only.
+
+A user-level timer interrupt is pending if the UTIP bit in the {\tt uip}
+register is set.  User-level timer interrupts are disabled when the UTIE
+bit in the {\tt uie} register is clear.  The ABI should provide a
+mechanism to clear a pending timer interrupt.
+
+A user-level external interrupt is pending if the UEIP bit in the
+{\tt uip} register is set.  User-level external interrupts are disabled
+when the UEIE bit in the {\tt uie} register is clear.  The ABI
+should provide facilities to mask, unmask, and query the cause of external
+interrupts.
+
+The {\tt uip} and {\tt uie} registers are subsets of the {\tt mip} and {\tt
+mie} registers.
+Reading any field, or writing any writable field, of {\tt uip}/{\tt uie}
+effects a read or write of the homonymous field of {\tt mip}/{\tt mie}.
+If S-mode is implemented, the {\tt uip} and {\tt uie} registers are also
+subsets of the {\tt sip} and {\tt sie} registers.
+
+\subsection{Machine Trap Delegation Registers ({\tt medeleg} and {\tt mideleg})}
+
+In systems with the N extension, the {\tt medeleg} and {\tt mideleg}
+registers, described in Chapter~\ref{machine},  must be implemented.
+
+In systems that implement S-mode, {\tt medeleg} and {\tt mideleg}
+behave as described in Chapter~\ref{machine}.
+In systems with only M and U privilege modes, setting a bit in {\tt medeleg}
+or {\tt mideleg} delegates the corresponding trap in U-mode to the U-mode trap
+handler.
+
+\subsection{Supervisor Trap Delegation Registers ({\tt sedeleg} and {\tt sideleg})}
+
+For systems with both S-mode and the N extension, new CSRs {\tt
+sedeleg} and {\tt sideleg} are added.
+These registers have the same layout as the machine trap delegation registers,
+{\tt medeleg} and {\tt mideleg}.
+
+{\tt sedeleg} and {\tt sideleg} allow S-mode to delegate traps to U-mode.
+Only bits corresponding to traps that have been delegated to S-mode are
+writable; the others are hardwired to zero.
+Setting a bit in {\tt sedeleg} or {\tt sideleg} delegates the corresponding
+trap in U-mode to the U-mode trap handler.
+
+\subsection{Other CSRs}
+
+The {\tt uscratch}, {\tt uepc}, {\tt ucause}, {\tt utvec}, and {\tt utval}
+CSRs are defined analogously to the {\tt mscratch}, {\tt mepc}, {\tt mcause},
+{\tt mtvec}, and {\tt mtval} CSRs.
 
 \begin{commentary}
-  A more complete writeup to follow.
+  A more complete writeup is to follow.
 \end{commentary}
 
 \section{N Extension Instructions}
diff --git a/src/preface.tex b/src/preface.tex
index 0d3dd66..8d62d2b 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -40,7 +40,6 @@ The document contains the following versions of the RISC-V ISA modules:
     \em T          & \em 0.0 & \em Draft \\
     \em P          & \em 0.2 & \em Draft \\
     \em V          & \em 0.7 & \em Draft \\
-    \em N          & \em 1.1 & \em Draft \\
     \em Zam        & \em 0.1 & \em Draft \\
     \hline
   \end{tabular}
@@ -53,6 +52,7 @@ The changes in this version of the document include:
 \parskip 0pt
 \itemsep 1pt
 \item Defined big-endian ISA variant.
+\item Moved N extension for user-mode interrupts into Volume II.
 \end{itemize}
 
 \section*{Preface to Document Version 20190608-Base-Ratified}
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index dad890b..fe78bab 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -1,4 +1,5 @@
 \chapter{Control and Status Registers (CSRs)}
+\label{chap:priv-csrs}
 
 The SYSTEM major opcode is used to encode all privileged instructions
 in the RISC-V ISA.  These can be divided into two main classes: those
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 709f390..1a5fcc0 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -15,6 +15,7 @@ modules:
     \em Machine ISA    & \em 1.12 & \em Draft \\
     \em Supervisor ISA & \em 1.12 & \em Draft \\
     \em Hypervisor ISA & \em 0.4  & \em Draft \\
+    \em N Extension    & \em 1.1 & \em Draft \\
     \hline
   \end{tabular}
 \end{table}
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
index 1b0bb0a..edefe3a 100644
--- a/src/riscv-privileged.tex
+++ b/src/riscv-privileged.tex
@@ -78,6 +78,7 @@ Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \privmonthyear.
 \input{machine}
 \input{supervisor}
 \input{hypervisor}
+\input{n}
 \input{priv-insns}
 
 \input{priv-history}
diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex
index 1d4bd7f..ef25ca2 100644
--- a/src/riscv-spec.tex
+++ b/src/riscv-spec.tex
@@ -95,7 +95,6 @@ Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \specmonthyear.
 \input{t}
 \input{p}
 \input{v}
-\input{n}
 \input{zam}
 \input{ztso}
 \input{gmaps}
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 4173456..ba29386 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -25,7 +25,7 @@ A number of CSRs are provided for the supervisor.
 The supervisor should only view CSR state that should be visible to a
 supervisor-level operating system.  In particular, there is no
 information about the existence (or non-existence) of higher privilege
-levels (hypervisor or machine) visible in the CSRs accessible by the
+levels (machine level or other) visible in the CSRs accessible by the
 supervisor.
 
 Many supervisor CSRs are a subset of the equivalent machine-mode CSR,
@@ -47,7 +47,7 @@ register keeps track of the processor's current operating state.
 \begin{center}
 \setlength{\tabcolsep}{4pt}
 \scalebox{0.95}{
-\begin{tabular}{cWcccccWcccccWcc}
+\begin{tabular}{cWcccccWccccWcc}
 \\
 \instbit{31} &
 \instbitrange{30}{20} &
@@ -61,8 +61,7 @@ register keeps track of the processor's current operating state.
 \instbit{7} &
 \instbit{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
@@ -78,13 +77,12 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE}  &
-\multicolumn{1}{c|}{UIE}
+\multicolumn{1}{c|}{\wpri}
 \\
 \hline
-1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
+1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}}
 \end{center}
 }
@@ -97,7 +95,7 @@ register keeps track of the processor's current operating state.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{cScScccc}
+\begin{tabular}{cMFScccc}
 \\
 \instbit{SXLEN-1} &
 \instbitrange{SXLEN-2}{34} &
@@ -110,7 +108,7 @@ register keeps track of the processor's current operating state.
 \hline
 \multicolumn{1}{|c|}{SD} &
 \multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{UXL} &
+\multicolumn{1}{c|}{UXL[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{MXR} &
 \multicolumn{1}{c|}{SUM} &
@@ -119,7 +117,7 @@ register keeps track of the processor's current operating state.
 \hline
 1 & SXLEN-35 & 2 & 12 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cccccccccccc}
+\begin{tabular}{cWWFccccWcc}
 \\
 &
 \instbitrange{16}{15} &
@@ -129,25 +127,23 @@ register keeps track of the processor's current operating state.
 \instbit{7} &
 \instbit{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
  &
-\multicolumn{1}{c|}{XS[1:0]} &
-\multicolumn{1}{|c|}{FS[1:0]} &
+\multicolumn{1}{|c|}{XS[1:0]} &
+\multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
-\multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
-\multicolumn{1}{c|}{UIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
- & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
+ & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -174,13 +170,6 @@ trapping into supervisor mode.  When a trap is taken into supervisor
 mode, SPIE is set to SIE, and SIE is set to 0.  When an SRET instruction is
 executed, SIE is set to SPIE, then SPIE is set to 1.
 
-The UIE bit enables or disables user-mode interrupts.  User-level interrupts
-are enabled only if UIE is set and the hart is running in user-mode.  The UPIE
-bit indicates whether user-level interrupts were enabled prior to taking
-a user-level trap.  When a URET instruction is executed, UIE is
-set to UPIE, and UPIE is set to 1.  User-level interrupts are optional.  If
-omitted, the UIE and UPIE bits are hardwired to zero.
-
 \begin{commentary}
 The {\tt sstatus} register is a subset of the {\tt mstatus} register.  In
 a straightforward implementation, reading or writing any field in {\tt
@@ -188,7 +177,7 @@ sstatus} is equivalent to reading or writing the homonymous field in
 {\tt mstatus}.
 \end{commentary}
 
-\subsection{Base ISA Control in {\tt sstatus} Register}
+\subsubsection{Base ISA Control in {\tt sstatus} Register}
 
 The UXL field controls the value of XLEN for U-mode, termed {\em UXLEN},
 which may differ from the value of XLEN for S-mode, termed {\em SXLEN}.  The
@@ -208,7 +197,7 @@ effective addresses are taken modulo $2^{UXLEN}$.  For example, when UXLEN=32
 and SXLEN=64, user-mode memory accesses reference the lowest \wunits{4}{GiB}
 of the address space.
 
-\subsection{Memory Privilege in {\tt sstatus} Register}
+\subsubsection{Memory Privilege in {\tt sstatus} Register}
 \label{sec:sum}
 
 The MXR (Make eXecutable Readable) bit modifies the privilege with which loads
@@ -247,7 +236,7 @@ instruction page-fault handler to direct supervisor software to use the
 alternate mapping.
 \end{commentary}
 
-\subsection{Endianness Control in {\tt sstatus} Register}
+\subsubsection{Endianness Control in {\tt sstatus} Register}
 
 The UBE bit is a \warl\ field that controls the endianness of explicit
 memory accesses made from U-mode, which may differ from the endianness of
@@ -330,14 +319,6 @@ a supervisor-mode timer interrupt (see Table~\ref{scauses}) causes the {\tt pc}
 to be set to BASE+{\tt 0x14}.
 Setting MODE=Vectored may impose a stricter alignment constraint on BASE.
 
-\begin{commentary}
-When vectored interrupts are enabled, interrupt cause 0, which corresponds to
-user-mode software interrupts, are vectored to the same location as
-synchronous exceptions.  This ambiguity does not arise in practice for
-supervisor software, since user-mode software interrupts are either disabled
-or delegated to user mode.
-\end{commentary}
-
 \subsection{Supervisor Interrupt Registers ({\tt sip} and {\tt sie})}
 
 The {\tt sip} register is an SXLEN-bit read/write register containing
@@ -348,28 +329,24 @@ SXLEN-bit read/write register containing interrupt enable bits.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{EccFccFcc}
+\begin{tabular}{KcFcFcc}
 \instbitrange{SXLEN-1}{10} &
 \instbit{9} &
-\instbit{8} &
-\instbitrange{7}{6} &
+\instbitrange{8}{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
 \multicolumn{1}{|c|}{\wpri} &
 \multicolumn{1}{c|}{SEIP} &
-\multicolumn{1}{c|}{UEIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIP} &
-\multicolumn{1}{c|}{UTIP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIP} &
-\multicolumn{1}{c|}{USIP} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-SXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
+SXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -382,28 +359,24 @@ SXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{EccFccFcc}
+\begin{tabular}{KcFcFcc}
 \instbitrange{SXLEN-1}{10} &
 \instbit{9} &
-\instbit{8} &
-\instbitrange{7}{6} &
+\instbitrange{8}{6} &
 \instbit{5} &
-\instbit{4} &
-\instbitrange{3}{2} &
+\instbitrange{4}{2} &
 \instbit{1} &
 \instbit{0} \\
 \hline
 \multicolumn{1}{|c|}{\wpri} &
 \multicolumn{1}{c|}{SEIE} &
-\multicolumn{1}{c|}{UEIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{STIE} &
-\multicolumn{1}{c|}{UTIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SSIE} &
-\multicolumn{1}{c|}{USIE} \\
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-SXLEN-10 & 1 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
+SXLEN-10 & 1 & 3 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -424,57 +397,19 @@ Interprocessor interrupts are sent to other harts by implementation-specific
 means, which will ultimately cause the SSIP bit to be set in the recipient
 hart's {\tt sip} register.
 
-A user-level software interrupt is triggered on the current hart by writing
-1 to its user software interrupt-pending (USIP) bit in the {\tt sip} register.
-A pending user-level software interrupt can be cleared by writing 0 to the
-USIP bit in {\tt sip}.  User-level software interrupts are disabled when the
-USIE bit in the {\tt sie} register is clear.  If user-level interrupts are not
-supported, USIP and USIE are hardwired to zero.
-
-All bits besides SSIP, USIP, and UEIP in the {\tt sip} register are read-only.
+All bits besides SSIP in the {\tt sip} register are read-only.
 
 A supervisor-level timer interrupt is pending if the STIP bit in the {\tt sip}
 register is set.  Supervisor-level timer interrupts are disabled when the STIE
 bit in the {\tt sie} register is clear.  The implementation must provide a
 mechanism to clear a pending timer interrupt.
 
-A user-level timer interrupt is pending if the UTIP bit in the {\tt sip}
-register is set.  User-level timer interrupts are disabled when the UTIE bit
-in the {\tt sie} register is clear.  If user-level interrupts are supported,
-the ABI should provide a facility for scheduling timer interrupts in terms of
-real-time counter values.  If user-level interrupts are not supported, UTIP
-and UTIE are hardwired to zero.
-
 A supervisor-level external interrupt is pending if the SEIP bit in the
 {\tt sip} register is set.  Supervisor-level external interrupts are disabled
 when the SEIE bit in the {\tt sie} register is clear.  The implementation
 should provide facilities to mask, unmask, and query the cause of external
 interrupts.
 
-The UEIP field in {\tt sip} contains a single read-write bit.  UEIP
-may be written by S-mode software to indicate to U-mode that an
-external interrupt is pending.  Additionally, the platform-level
-interrupt controller may generate user-level external interrupts.  The
-logical-OR of the software-writable bit and the signal from the
-external interrupt controller are used to generate external interrupts
-for user mode.  When the UEIP bit is read with a CSRRW, CSRRS, or
-CSRRC instruction, the value returned in the {\tt rd} destination
-register contains the logical-OR of the software-writable bit and the
-interrupt signal from the interrupt controller.  However, the value
-used in the read-modify-write sequence of a CSRRS or CSRRC instruction
-is only the software-writable UEIP bit, ignoring the interrupt value
-from the external interrupt controller.
-
-\begin{commentary}
-  Analogous to SEIP, the UEIP field behavior is designed to allow a
-  higher privilege layer to mimic external interrupts without losing
-  any real external interrupts.
-\end{commentary}
-
-User-level external interrupts are disabled when the UEIE bit in the {\tt sie}
-register is clear.  If the N extension for user-level interrupts is not
-implemented, UEIP and UEIE are hardwired to zero.
-
 \begin{commentary}
 The {\tt sip} and {\tt sie} registers are subsets of the {\tt mip} and {\tt
 mie} registers.  Reading any field, or writing any writable field, of {\tt
@@ -657,16 +592,14 @@ so is only guaranteed to hold supported exception codes.
   \hline
   Interrupt & Exception Code  & Description \\
   \hline	 
-  1         & 0               & User software interrupt \\
+  1         & 0               & {\em Reserved} \\
   1         & 1               & Supervisor software interrupt \\
-  1         & 2--3            & {\em Reserved for future standard use} \\ \hline
-  1         & 4               & User timer interrupt \\
+  1         & 2--4            & {\em Reserved} \\
   1         & 5               & Supervisor timer interrupt \\
-  1         & 6--7            & {\em Reserved for future standard use} \\ \hline
-  1         & 8               & User external interrupt \\
+  1         & 6--8            & {\em Reserved} \\
   1         & 9               & Supervisor external interrupt \\
-  1         & 10--15          & {\em Reserved for future standard use} \\
-  1         & $\ge$16         & {\em Reserved for platform use} \\ \hline
+  1         & 10--15          & {\em Reserved} \\
+  1         & $\ge$16         & {\em Available for platform use} \\ \hline
   0         & 0               & Instruction address misaligned \\
   0         & 1               & Instruction access fault \\
   0         & 2               & Illegal instruction \\   
@@ -677,16 +610,16 @@ so is only guaranteed to hold supported exception codes.
   0         & 7               & Store/AMO access fault \\
   0         & 8               & Environment call from U-mode \\
   0         & 9               & Environment call from S-mode \\
-  0         & 10--11          & {\em Reserved for future standard use} \\
+  0         & 10--11          & {\em Reserved} \\
   0         & 12              & Instruction page fault \\
   0         & 13              & Load page fault \\
-  0         & 14              & {\em Reserved for future standard use} \\
+  0         & 14              & {\em Reserved} \\
   0         & 15              & Store/AMO page fault \\
-  0         & 16--23          & {\em Reserved for future standard use} \\
-  0         & 24--31          & {\em Reserved for custom use} \\
-  0         & 32--47          & {\em Reserved for future standard use} \\
-  0         & 48--63          & {\em Reserved for custom use} \\
-  0         & $\ge$64         & {\em Reserved for future standard use} \\
+  0         & 16--23          & {\em Reserved} \\
+  0         & 24--31          & {\em Available for custom use} \\
+  0         & 32--47          & {\em Reserved} \\
+  0         & 48--63          & {\em Available for custom use} \\
+  0         & $\ge$64         & {\em Reserved} \\
   \hline
 \end{tabular}
 \end{center}