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| author | Andrew Waterman <andrew@sifive.com> | 2019-10-11 15:55:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-11 15:55:01 -0700 |
| commit | f8270a138f8fa3e9770fd28d2e3207fb0021de50 (patch) | |
| tree | 217bc164ec2cb6a69bb44a443f6372c2a4ffb9e2 | |
| parent | 057366db9a4241d6e6ee2a711da7201b1993a2c4 (diff) | |
| download | riscv-isa-manual-f8270a138f8fa3e9770fd28d2e3207fb0021de50.zip riscv-isa-manual-f8270a138f8fa3e9770fd28d2e3207fb0021de50.tar.gz riscv-isa-manual-f8270a138f8fa3e9770fd28d2e3207fb0021de50.tar.bz2 | |
Explicitly remark that SUM/MXR changes don't need an SFENCE.VMA
| -rw-r--r-- | src/supervisor.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 3e6ec73..25f00f1 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1058,6 +1058,9 @@ register, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively. +Changes to the {\tt sstatus} fields SUM and MXR take effect immediately, +without the need to execute an SFENCE.VMA instruction. + \begin{commentary} The following common situations typically require executing an SFENCE.VMA instruction: |