Describe what we mean by endianness

2 files changed, 24 insertions, 4 deletions

diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex
index edda91b..298a0d2 100644
--- a/src/riscv-spec.tex
+++ b/src/riscv-spec.tex
@@ -36,7 +36,7 @@ Arvind, Krste Asanovi\'{c}, Rimas Avi\v{z}ienis, Jacob Bachmeyer, Christopher
 F. Batten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs,
 Christopher Celio, Chuanhua Chang, David Chisnall, Paul Clayton, Palmer
 Dabbelt, Ken Dockser, Roger Espasa, Shaked Flur, Stefan Freudenberger,
-Marc Gauthier, Jan Gray, Michael Hamburg,
+Marc Gauthier, Andy Glew, Jan Gray, Michael Hamburg,
 John Hauser, David Horner, Bruce Hoult, Bill Huffman, Alexandre Joannou,
 Olof Johansson, Ben Keller, David Kruckemyer, Yunsup Lee,
 Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget, Margaret
diff --git a/src/rv32.tex b/src/rv32.tex
index 1548dc0..78742cb 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -984,14 +984,34 @@ compressed instruction-set extension, C.
 RV32I is a load-store architecture, where only load and store
 instructions access memory and arithmetic instructions only operate on
 CPU registers.  RV32I provides a 32-bit address space that is
-byte-addressed.  The EEI will define whether the memory system is
-little-endian or big-endian.  The EEI will
-define what portions of the address space are legal to access with
+byte-addressed.
+The EEI will define what portions of the address space are legal to access with
 which instructions (e.g., some addresses might be read only, or
 support word access only).  Loads with a destination of {\tt x0} must
 still raise any exceptions and cause any other side effects even
 though the load value is discarded.
 
+The EEI will define whether the memory system is little-endian or big-endian.
+In RISC-V, endianness is byte-address invariant.
+\begin{commentary}
+In a system for which endianness is byte-address invariant, the following
+property holds: if a byte is stored to memory at some address in some
+endianness, then a byte-sized load from that address in any endianness returns
+the stored value.
+
+In a little-endian configuration, multibyte stores write the least-significant
+register byte at the lowest memory byte address, followed by the other
+register bytes in ascending order of their significance.
+Loads similarly transfer the contents of the lesser memory byte addresses to
+the less-significant register bytes.
+
+In a big-endian configuration, multibyte stores write the most-significant
+register byte at the lowest memory byte address, followed by the other
+register bytes in descending order of their significance.
+Loads similarly transfer the contents of the greater memory byte addresses to
+the less-significant register bytes.
+\end{commentary}
+
 \vspace{-0.4in}
 \begin{center}
 \begin{tabular}{M@{}R@{}F@{}R@{}O}