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| author | Andrew Waterman <andrew@sifive.com> | 2019-12-27 19:32:43 -0600 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-12-27 19:32:43 -0600 |
| commit | a6c204f6e9aad024e32cc999bcc83c88a6e3f571 (patch) | |
| tree | e72a579fd399c6285fbd6a93b30c3b896fc600a5 | |
| parent | 5aa7d7dd27d080a9822f588835ed88ced697dee8 (diff) | |
| download | riscv-isa-manual-a6c204f6e9aad024e32cc999bcc83c88a6e3f571.zip riscv-isa-manual-a6c204f6e9aad024e32cc999bcc83c88a6e3f571.tar.gz riscv-isa-manual-a6c204f6e9aad024e32cc999bcc83c88a6e3f571.tar.bz2 | |
Fix FENCE.I cross-reference
| -rw-r--r-- | src/memory.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/memory.tex b/src/memory.tex index 5444b5c..08fca50 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -801,7 +801,7 @@ Consider Figure~\ref{fig:litmus:addrpo}: RVWMO does not currently attempt to formally describe how FENCE.I, SFENCE.VMA, I/O fences, and PMAs behave. All of these behaviors will be described by future formalizations. -In the meantime, the behavior of FENCE.I is described in Section~\ref{sec:fence}, the behavior of SFENCE.VMA is described in the RISC-V Instruction Set Privileged Architecture Manual, and the behavior of I/O fences and the effects of PMAs are described below. +In the meantime, the behavior of FENCE.I is described in Chapter~\ref{chap:zifencei}, the behavior of SFENCE.VMA is described in the RISC-V Instruction Set Privileged Architecture Manual, and the behavior of I/O fences and the effects of PMAs are described below. \subsection{Coherence and Cacheability} |