Add a description of the reservability PMA.

1 files changed, 32 insertions, 9 deletions

diff --git a/src/machine.tex b/src/machine.tex
index baacef9..176f931 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2699,16 +2699,17 @@ memory supports page-table walks.
 
 Atomicity PMAs describes which atomic instructions are supported in
 this address region.
-Main memory and I/O regions may only support a subset or none of the
-processor-supported atomic operations.
+Support for atomic instructions is divided into two
+categories: {\em LR/SC} and {\em AMOs}.
 
 \begin{commentary}
 Some platforms might mandate that all of cacheable main memory support
 all atomic operations required by the attached processors.
 \end{commentary}
 
-Support for atomic instructions is divided into two categories: {\em
-  LR/SC} and {\em AMOs}. Within AMOs, there are four levels of
+\subsubsection{AMO PMA}
+
+  Within AMOs, there are four levels of
 support: {\em AMONone}, {\em AMOSwap}, {\em AMOLogical}, and {\em
   AMOArithmetic}.  AMONone indicates that no AMO operations are
 supported.  AMOSwap indicates that only {\tt amoswap} instructions are
@@ -2718,6 +2719,8 @@ instructions plus all the logical AMOs ({\tt amoand}, {\tt amoor},
 AMOs are supported.  For each level of support, naturally aligned AMOs
 of a given width are supported if the underlying memory region
 supports reads and writes of that width.
+Main memory and I/O regions may only support a subset or none of the
+processor-supported atomic operations.
 
 \begin{table*}[h!]
 \begin{center}
@@ -2738,14 +2741,34 @@ supports reads and writes of that width.
 
 \begin{commentary}
 We recommend providing at least AMOLogical support for I/O regions
+where possible.
+\end{commentary}
+
+\subsubsection{Reservability PMA}
+
+For {\em LR/SC}, there are three levels of support indicating combinations of
+the reservability and eventuality properties:  {\em RsrvNone},
+{\em RsrvNonEventual}, and {\em RsrvEventual}.
+RsrvNone indicates that no LR/SC operations are supported (the location is
+non-reservable).  RsrvNonEventual indicates that the operations are supported
+(the location is reservable), but without the eventual success guarantee
+described in the unprivileged ISA specification.  RsrvEventual indicates that
+the operations are supported and provide the eventual success guarantee.
+
+\begin{commentary}
+We recommend providing RsrvEventual support for main memory regions
 where possible.  Most I/O regions will not support LR/SC accesses, as
-these are most conveniently built on top of a cache-coherence scheme.
+these are most conveniently built on top of a cache-coherence scheme, but some
+may support RsrvNonEventual or RsrvEventual.
+\end{commentary}
+
+\begin{commentary}
+When LR/SC is used for memory locations marked RsrvNonEventual, software should
+provide alternative fall-back mechanisms used when lack of progress is
+detected.
 \end{commentary}
 
-Memory regions that support LR/SC will define the conditions under which LR/SC
-sequences must succeed or must fail.  Main memory must guarantee the eventual
-success of any LR/SC sequence that meets the requirements described in the
-user ISA specification.
+\subsubsection{Alignment}
 
 Memory regions that support aligned LR/SC or aligned AMOs might also support
 misaligned LR/SC or misaligned AMOs for some addresses and access widths.  If,