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| author | Andrew Waterman <andrew@sifive.com> | 2020-01-06 12:08:09 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-01-06 12:08:30 -0800 |
| commit | 63451c0a81e9d8f7ebc270dbb2533999df297388 (patch) | |
| tree | 00a67d0f23941626bbbfb7c6f0b186e8e0593b57 | |
| parent | a6c204f6e9aad024e32cc999bcc83c88a6e3f571 (diff) | |
| download | riscv-isa-manual-63451c0a81e9d8f7ebc270dbb2533999df297388.zip riscv-isa-manual-63451c0a81e9d8f7ebc270dbb2533999df297388.tar.gz riscv-isa-manual-63451c0a81e9d8f7ebc270dbb2533999df297388.tar.bz2 | |
Make mtimecmp code sequence legal
Closes #472
| -rw-r--r-- | src/machine.tex | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex index c41b7ea..9058403 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1690,9 +1690,10 @@ to the intermediate value of the comparand: \begin{verbatim} # New comparand is in a1:a0. li t0, -1 - sw t0, mtimecmp # No smaller than old value. - sw a1, mtimecmp+4 # No smaller than new value. - sw a0, mtimecmp # New value. + la t1, mtimecmp + sw t0, 0(t1) # No smaller than old value. + sw a1, 4(t1) # No smaller than new value. + sw a0, 0(t1) # New value. \end{verbatim} \end{center} \caption{Sample code for setting the 64-bit time comparand in RV32, assuming |