Update preface

1 files changed, 22 insertions, 12 deletions

diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index a0cd8e3..2840066 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -23,30 +23,40 @@ modules:
 
 The Machine and Supervisor ISAs, version 1.11, have been ratified by
 the RISC-V Foundation.  Version 1.12 of these modules, described in
-this document, is backwards compatible with version 1.11.
+this document, is a minor revision to version 1.11.
 
-Changes from version 1.11 include:
+The following changes have been made since version 1.11, which, while not
+strictly backwards compatible, are not anticipated to cause software
+portability problems in practice:
 \vspace{-0.2in}
 \begin{itemize}
   \parskip 0pt
   \itemsep 1pt
-\item Defined the RV32-only CSR {\tt mstatush}, which contains most of the
-  same fields as the upper 32 bits of RV64's {\tt mstatus}.
-\item Relaxed I/O regions have been specified to follow RVWMO.  The previous
-  specification implied that PPO rules other than fences and acquire/release
-  annotations did not apply.
 \item Changed MRET and SRET to clear {\tt mstatus}.MPRV when leaving M-mode.
-\item Revised the hypervisor architecture proposal to represent VS-mode CSR
-  state more simply.
-\item Permitted the unconditional delegation of less-privileged interrupts.
+\item Reserved additional {\tt satp} patterns for future use.
 \item Stated that the {\tt scause} Exception Code field must implement
   bits 4--0 at minimum.
-\item Reserved additional {\tt satp} patterns for future use.
-\item Added optional big-endian and bi-endian support.
+\item Relaxed I/O regions have been specified to follow RVWMO.  The previous
+  specification implied that PPO rules other than fences and acquire/release
+  annotations did not apply.
 \item Constrained the LR/SC reservation set size and shape when using
   page-based virtual memory.
 \end{itemize}
 
+Additionally, the following compatible changes have been made since version
+1.11:
+\vspace{-0.2in}
+\begin{itemize}
+  \parskip 0pt
+  \itemsep 1pt
+\item Defined the RV32-only CSR {\tt mstatush}, which contains most of the
+  same fields as the upper 32 bits of RV64's {\tt mstatus}.
+\item Permitted the unconditional delegation of less-privileged interrupts.
+\item Added optional big-endian and bi-endian support.
+\end{itemize}
+
+Finally, the hypervisor architecture proposal has been extensively revised.
+
 \newpage
 
 \section*{Preface to Version 1.11}