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| author | Thomas Wicki <35509028+tmw-wdc@users.noreply.github.com> | 2020-01-09 16:11:23 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-01-09 16:11:23 -0800 |
| commit | 1ca47c3bfe1ddb70816b5fff7ffe834054709c69 (patch) | |
| tree | 326826a987715a7ec5d4ff5e42d0e7274c41c5d5 | |
| parent | 6cb49a42429616cdcf343f70e1ab41e2dbaaa13d (diff) | |
| download | riscv-isa-manual-1ca47c3bfe1ddb70816b5fff7ffe834054709c69.zip riscv-isa-manual-1ca47c3bfe1ddb70816b5fff7ffe834054709c69.tar.gz riscv-isa-manual-1ca47c3bfe1ddb70816b5fff7ffe834054709c69.tar.bz2 | |
Add Western Digital's SweRV EL2 and EH2 cores (#474)
Western Digital's second generation cores SweRV EL2 and EH2
| -rw-r--r-- | marchid.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -33,3 +33,5 @@ MSCC | Rongcui Dong | [Rongcui Dong](mailto:rongcuid BlackParrot | The World | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 13 | https://github.com/black-parrot BaseJump Manycore | U. Washington | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 14 | https://github.com/bespoke-silicon-group/bsg_manycore C-Class | IIT Madras | [Neel Gala](mailto:neelgala@gmail.com) | 15 | https://gitlab.com/shaktiproject/cores/c-class +SweRV EL2 | Western Digital Corporation | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com) | 16 | https://github.com/chipsalliance/Cores-SweRV-EL2 +SweRV EH2 | Western Digital Corporation | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com) | 17 | https://github.com/chipsalliance/Cores-SweRV-EH2 |