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authorAndrew Waterman <andrew@sifive.com>2019-10-02 17:24:04 +0200
committerAndrew Waterman <andrew@sifive.com>2019-10-02 17:25:50 +0200
commitef917313d97d89b43a799d0ed12193b498c233f5 (patch)
treebaaf3f24710dbe842859743d17fd62f1e10ed92b
parent9a1fe02e8a435dc5742b0f590df2576cb55a1676 (diff)
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riscv-isa-manual-lrsc.tar.gz
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Address some of Derek's feedbacklrsc
-rw-r--r--src/a.tex19
1 files changed, 4 insertions, 15 deletions
diff --git a/src/a.tex b/src/a.tex
index a2a6f87..414210d 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -208,8 +208,10 @@ The platform should provide a means to determine the size and shape of the
reservation set.
A platform specification may constrain the size and shape of the reservation
-set. For example, the Unix platform is expected to require the set be
-contiguous and no greater than the virtual memory page size.
+set.
+For example, the Unix platform is expected to require of main memory that the
+reservation set be of fixed size, contiguous, naturally aligned, and no
+greater than the virtual memory page size.
\end{commentary}
\begin{commentary}
@@ -229,19 +231,6 @@ an SC can only pair with the most recent LR, and LR with the next
following SC, in program order. This is a restriction to the
Atomicity Axiom in Section~\ref{sec:rvwmo} that ensures software runs
correctly on expected common implementations that operate in this manner.
-
-It is conceivable for a future extension to allow the same hart to hold
-multiple independent reservations at once, such as to help improve performance
-in some scenarios. Such an extension would presumably introduce a mechanism
-to clear all of a hart's reservations, replacing the no longer effective SC
-to a scratch word. The practicality of such an extension is not established.
-\end{commentary}
-
-\begin{commentary}
-Another example effective memory write that invalidates a reservation
-is the invalidation of a dirty cache line. It is also possible for
-operations that prepare for a write without actually doing the write
-to also invalidate a reservation, such as prefetch-for-write requests.
\end{commentary}
An SC instruction can never be observed by another RISC-V hart