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author | elisa <elisa@riscv.org> | 2021-10-01 10:07:41 -0700 |
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committer | elisa <elisa@riscv.org> | 2021-10-01 10:07:41 -0700 |
commit | f933f3d3ce4770a36c40ab6d1fa1554e392f89cf (patch) | |
tree | 832226b280e2e1cd9e2150b7a80a68ff86576593 | |
parent | 2542e5b8c751e9de660b63445a0e12c7bbbea948 (diff) | |
parent | e511c4664368355e6d85b8e487fdfdc5d7de44e4 (diff) | |
download | riscv-isa-manual-f933f3d3ce4770a36c40ab6d1fa1554e392f89cf.zip riscv-isa-manual-f933f3d3ce4770a36c40ab6d1fa1554e392f89cf.tar.gz riscv-isa-manual-f933f3d3ce4770a36c40ab6d1fa1554e392f89cf.tar.bz2 |
Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adoc
-rw-r--r-- | src/rv32.tex | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 99d58f7..70e27d6 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1266,7 +1266,7 @@ The fence mode field {\em fm} defines the semantics of the FENCE. A FENCE with {\em fm}=0000 orders all memory operations in its predecessor set before all memory operations in its successor set. -The optional FENCE.TSO instruction is encoded as a FENCE instruction +The FENCE.TSO instruction is encoded as a FENCE instruction with {\em fm}=1000, {\em predecessor}=RW, and {\em successor}=RW. FENCE.TSO orders all load operations in its predecessor set before all memory operations in its @@ -1276,10 +1276,9 @@ operations in the FENCE.TSO's predecessor set unordered with non-AMO loads in its successor set. \begin{commentary} - The FENCE.TSO encoding was added as an optional extension to the - original base FENCE instruction encoding. The base definition - requires that implementations ignore any set bits and treat the - FENCE as global, and so this is a backwards-compatible extension. + Because \mbox{FENCE RW,RW} imposes a superset of the orderings that + FENCE.TSO imposes, it is correct to ignore the {\em fm} field and + implement FENCE.TSO as \mbox{FENCE RW,RW}. \end{commentary} The unused fields in the FENCE instructions---{\em rs1} and {\em rd}---are |