fixed a few convert problems

2 files changed, 42 insertions, 39 deletions

diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index 13c2388..79904d8 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -895,21 +895,27 @@ the architectural state, either because _rd_=`x0` (e.g.
 C.ADD _x0_, _t0_), or because _rd_ is overwritten with a copy of itself
 (e.g. C.ADDI _t0_, 0).
 
+[NOTE]
+====
 This HINT encoding has been chosen so that simple implementations can
 ignore HINTs altogether, and instead execute a HINT as a regular
 computational instruction that happens not to mutate the architectural
 state.
+====
 
 RVC HINTs do not necessarily expand to their RVI HINT counterparts. For
 example, C.ADD _x0_, _t0_ might not encode the same HINT as
 ADD _x0_, _x0_, _t0_.
 
+[NOTE]
+====
 The primary reason to not require an RVC HINT to expand to an RVI HINT
 is that HINTs are unlikely to be compressible in the same manner as the
 underlying computational instruction. Also, decoupling the RVC and RVI
 HINT mappings allows the scarce RVC HINT space to be allocated to the
 most popular HINTs, and in particular, to HINTs that are amenable to
 macro-op fusion.
+====
 
 <<rvc-t-hints>> lists all RVC HINT code points. For RV32C, 78%
 of the HINT space is reserved for standard HINTs, but none are presently
@@ -921,31 +927,29 @@ no standard HINTs will ever be defined in this subspace.
 //[cols="<,<,>,<",options="header",]
 |===
 |Instruction |Constraints |Code Points |Purpose
-|C.NOP |_nzimm_latexmath:[$\neq$]0 |63 |_Reserved for future standard
+|C.NOP |_nzimm_latexmath:[$\neq$]0 |63 .6+^.>s|_Reserved for future standard
 use_
 
-|C.ADDI | |_rd_latexmath:[$\neq$]`x0`, _nzimm_=0 |31
+|C.ADDI | _rd_latexmath:[$\neq$]`x0`, _nzimm_=0 |31
 
-|C.LI | |_rd_=`x0` |64
+|C.LI | _rd_=`x0` |64
 
-|C.LUI | |_rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |63
+|C.LUI | _rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |63
 
-|C.MV | |_rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31
+|C.MV | _rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31
 
-|C.ADD | |_rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31
+|C.ADD | _rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31
 
-|C.SLLI |_rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |31 (RV32) |_Designated
+|C.SLLI |_rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |31 (RV32), 63 (RV64/128)  .5+^.>s|_Designated
 for custom use_
 
-| | |63 (RV64/128) |
+|C.SLLI64 | _rd_=`x0` |1
 
-|C.SLLI64 | |_rd_=`x0` |1
+|C.SLLI64 | _rd_latexmath:[$\neq$]`x0`, RV32 and RV64 only |31
 
-|C.SLLI64 | |_rd_latexmath:[$\neq$]`x0`, RV32 and RV64 only |31
+|C.SRLI64 | RV32 and RV64 only |8
 
-|C.SRLI64 | |RV32 and RV64 only |8
-
-|C.SRAI64 | |RV32 and RV64 only |8
+|C.SRAI64 | RV32 and RV64 only |8
 |===
 
 === RVC Instruction Set Listings
@@ -961,24 +965,23 @@ _Custom_ to indicate that the opcode is designated for custom
 extensions; or _HINT_ to indicate that the opcode is reserved for
 microarchitectural hints <<rvc-hints>>.
 
+[[rvcopcodemap]]
+.RVC opcode map instructions.
 //[cols=">,^,^,^,^,^,^,^,^,<",]
 |===
-|inst[15:13] |000 |001 |010 |011 |100 |101 |110 |111 |
-|inst[1:0] | | | | | | | | |
-| |ADDI4SPN |FLD |LW |FLW |_Reserved_ |FSD |SW |FSW |RV32
-| | |FLD | |LD | |FSD | |SD |RV64
-| | |LQ | |LD | |SQ | |SD |RV128
-|01 |ADDI |JAL |LI |LUI/ADDI16SP |MISC-ALU |J |BEQZ |BNEZ |RV32
-| | |ADDIW | | | | | | |RV64
-| | |ADDIW | | | | | | |RV128
-|10 |SLLI |FLDSP |LWSP |FLWSP |J[AL]R/MV/ADD |FSDSP |SWSP |FSWSP |RV32
-| | |FLDSP | |LDSP | |FSDSP | |SDSP |RV64
-| | |LQSP | |LDSP | |SQSP | |SDSP |RV128
-|11 |latexmath:[$>$]16b | | | | | | | |
+|inst[15:13] .2+^.>s|000 .2+^.>s|001 .2+^.>s|010 .2+^.>s|011 .2+^.>s|100 .2+^.>s|101 .2+^.>s|110 .2+^.>s|111 .2+^.>s|
+|inst[1:0]
+
+|00|ADDI4SPN |FLD FLD LQ | LW | FLW LD LD | _Reserved_ | FSD FSD SQSW | SW | FSW SD SD | RV32 RV64 RV128
+
+|01 |ADDI |JAL ADDIW ADDIW |LI |LUI/ADDI16SP |MISC-ALU |J |BEQZ |BNEZ |RV32 RV64 RV128
+
+|10 |SLLI |FLDSP FLDSP LDSP |LWSP |FLWSP LDSP LDSP |J[AL]R/MV/ADD |FSDSP FSDSP SQSP|SWSP |FSWSP SDSP SDSP|RV32 RV6 RV128
+
+|11 9+|latexmath:[$>$]16b
 |===
 
-<<rvc-instr-table0>>, <<rvc-instr-table1>>, and <<rvc-instr-table2>> list the
-RVC instructions.
+<<rvc-instr-table0>>, <<rvc-instr-table1>>, and <<rvc-instr-table2>> list the RVC instructions.
 
 [[rvc-instr-table0]]
 .Instruction listing for RVC, Quadrant 0
@@ -987,7 +990,7 @@ RVC instructions.
 
 |000|0 |  | | | | | |0 | | |00 |_Illegal instruction_
 
-|000|nzuimm[5:4latexmath:[$\vert$]9:6latexmath:[$\vert$]2latexmath:[$\vert$]3]
+|000|nzuimm[5:4 latexmath:[$\vert$]9:6latexmath:[$\vert$]2 latexmath:[$\vert$]3]
 | |  | | | | |rd latexmath:[$'$] | | |00 |C.ADDI4SPN _(RES,
 nzuimm=0)_
 
@@ -1019,7 +1022,7 @@ _(RV32)_
 |uimm[2latexmath:[$\vert$]6] | |rs2 latexmath:[$'$] | | |00 |C.SW
 
 |111|uimm[5:3] | |rs1 latexmath:[$'$] | |
-|uimm[2latexmath:[$\vert$]6] | |rs2 latexmath:[$'$] | | |00 |C.FSW
+|uimm[2 latexmath:[$\vert$]6] | |rs2 latexmath:[$'$] | | |00 |C.FSW
 _(RV32)_
 
 |111|uimm[5:3] | |rs1 latexmath:[$'$] | | |uimm[7:6] |
@@ -1033,7 +1036,7 @@ _(RV32)_
 |===
 
 |000  |nzimm[5] |0 | | | | |nzimm[4:0] | | | | |01 | |C.NOP _(HINT,
-nzimmlatexmath:[$\neq$]0)_
+nzimm latexmath:[$\neq$]0)_
 
 |000  |nzimm[5] |rs1/rdlatexmath:[$\neq$]0 | | | | |nzimm[4:0] | |
 | | |01 | |C.ADDI _(HINT, nzimm=0)_
@@ -1042,17 +1045,17 @@ nzimmlatexmath:[$\neq$]0)_
 |imm[11latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
 | | | | | | | | | | |01 | |C.JAL _(RV32)_
 
-|001  |imm[5] |rs1/rdlatexmath:[$\neq$]0 | | | | |imm[4:0] | | | |
+|001  |imm[5] |rs1/rd latexmath:[$\neq$]0 | | | | |imm[4:0] | | | |
 |01 | |C.ADDIW _(RV64/128; RES, rd=0)_
 
 |010  |imm[5] |rdlatexmath:[$\neq$]0 | | | | |imm[4:0] | | | | |01
 | |C.LI _(HINT, rd=0)_
 
 |011  |nzimm[9] |2 | | | |
-|nzimm[4latexmath:[$\vert$]6latexmath:[$\vert$]8:7latexmath:[$\vert$]5]
+|nzimm[4 latexmath:[$\vert$]6latexmath:[$\vert$]8:7latexmath:[$\vert$]5]
 | | | | |01 | |C.ADDI16SP _(RES, nzimm=0)_
 
-|011  |nzimm[17] |rdlatexmath:[$\neq$]latexmath:[$\{0,2\}$] | | | |
+|011  |nzimm[17] |rd latexmath:[$\neq$]latexmath:[$\{0,2\}$] | | | |
 |nzimm[16:12] | | | | |01 | |C.LUI _(RES, nzimm=0; HINT, rd=0)_
 
 |100  |nzuimm[5] |00 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | |
@@ -1093,15 +1096,15 @@ nzimmlatexmath:[$\neq$]0)_
 |100  |1 |11 | |— | | |11 | |— | | |01 | |_Reserved_
 
 |101
-|imm[11latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
+|imm[11 latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
 | | | | | | | | | | |01 | |C.J
 
 |110  |imm[8latexmath:[$\vert$]4:3] | | |rs1 latexmath:[$'$] | |
-|imm[7:6latexmath:[$\vert$]2:1latexmath:[$\vert$]5] | | | | |01 |
+|imm[7:6 latexmath:[$\vert$]2:1 latexmath:[$\vert$]5] | | | | |01 |
 |C.BEQZ
 
-|111  |imm[8latexmath:[$\vert$]4:3] | | |rs1 latexmath:[$'$] | |
-|imm[7:6latexmath:[$\vert$]2:1latexmath:[$\vert$]5] | | | | |01 |
+|111  |imm[8 latexmath:[$\vert$]4:3] | | |rs1 latexmath:[$'$] | |
+|imm[7:6 latexmath:[$\vert$]2:1 latexmath:[$\vert$]5] | | | | |01 |
 |C.BNEZ
 
 |===
@@ -1111,10 +1114,10 @@ nzimmlatexmath:[$\neq$]0)_
 //[cols="<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<",]
 |===
 
-|000  |nzuimm[5] |rs1/rdlatexmath:[$\neq$]0 | | | | |nzuimm[4:0] |
+|000  |nzuimm[5] |rs1/rd latexmath:[$\neq$]0 | | | | |nzuimm[4:0] |
 | | | |10 | |C.SLLI _(HINT, rd=0; RV32 Custom, nzuimm[5]=1)_
 
-|000  |0 |rs1/rdlatexmath:[$\neq$]0 | | | | |0 | | | | |10 |
+|000  |0 |rs1/rd latexmath:[$\neq$]0 | | | | |0 | | | | |10 |
 |C.SLLI64 _(RV128; RV32/64 HINT; HINT, rd=0)_
 
 |001  |uimm[5] |rd | | | | |uimm[4:3latexmath:[$\vert$]8:6] | | | |
diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf
index 0d03229..5230865 100644
--- a/src/riscv-isa-unpr-conv-review.pdf
+++ b/src/riscv-isa-unpr-conv-review.pdf