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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-06 18:05:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-06 18:05:22 -0700 |
| commit | 9292b6ed0533ac1c7e204b0054fac3a82a74ccc4 (patch) | |
| tree | 101bca218a16eee90e21a9dddea7326f23e15d78 | |
| parent | 4e220a3b35a95eced105194044350a4f13a24029 (diff) | |
| download | riscv-isa-manual-9292b6ed0533ac1c7e204b0054fac3a82a74ccc4.zip riscv-isa-manual-9292b6ed0533ac1c7e204b0054fac3a82a74ccc4.tar.gz riscv-isa-manual-9292b6ed0533ac1c7e204b0054fac3a82a74ccc4.tar.bz2 | |
Clarify mepc invalid address conversion
If any addresses are invalid, mepc must be able to hold at least one of them.
| -rw-r--r-- | src/machine.tex | 10 | ||||
| -rw-r--r-- | src/supervisor.tex | 10 |
2 files changed, 12 insertions, 8 deletions
diff --git a/src/machine.tex b/src/machine.tex index ffdc1a5..b50a934 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1907,8 +1907,9 @@ Though masked, {\tt mepc[1]} remains writable when IALIGN=32. {\tt mepc} is a \warl\ register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid -addresses. Implementations may convert some invalid address patterns into -other invalid addresses prior to writing them to {\tt mepc}. +addresses. +Prior to writing {\tt mepc}, implementations may convert an invalid address +into some other invalid address that {\tt mepc} is capable of holding. \begin{commentary} When address translation is not in effect, virtual addresses and physical @@ -2218,8 +2219,9 @@ bits are cleared to zero. If {\tt mtval} is not hardwired to zero, it is a \warl\ register that must be able to hold all valid virtual addresses and the value zero. It need not be capable of holding all -possible invalid addresses. Implementations may convert some invalid address -patterns into other invalid addresses prior to writing them to {\tt mtval}. +possible invalid addresses. +Prior to writing {\tt mtval}, implementations may convert an invalid address +into some other invalid address that {\tt mtval} is capable of holding. If the feature to return the faulting instruction bits is implemented, {\tt mtval} must also be able to hold all values less than $2^N$, where $N$ is the smaller of XLEN and ILEN. diff --git a/src/supervisor.tex b/src/supervisor.tex index 442e50d..f6c1737 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -621,8 +621,9 @@ Though masked, {\tt sepc[1]} remains writable when IALIGN=32. {\tt sepc} is a \warl\ register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid -addresses. Implementations may convert some invalid address patterns into -other invalid addresses prior to writing them to {\tt sepc}. +addresses. +Prior to writing {\tt sepc}, implementations may convert an invalid address +into some other invalid address that {\tt sepc} is capable of holding. When a trap is taken into S-mode, {\tt sepc} is written with the virtual address of the instruction that was interrupted or that @@ -790,8 +791,9 @@ bits are cleared to zero. {\tt stval} is a \warl\ register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all -possible invalid addresses. Implementations may convert some invalid address -patterns into other invalid addresses prior to writing them to {\tt stval}. +possible invalid addresses. +Prior to writing {\tt stval}, implementations may convert an invalid address +into some other invalid address that {\tt stval} is capable of holding. If the feature to return the faulting instruction bits is implemented, {\tt stval} must also be able to hold all values less than $2^N$, where $N$ is the smaller of XLEN and ILEN. |