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| author | Andrew Waterman <andrew@sifive.com> | 2021-05-01 18:07:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-02 16:46:30 -0700 |
| commit | 7453397cbf24033748214a45ea6bee0bca64065a (patch) | |
| tree | 6d97abb938c9aa912cf13526b28548f57e81f171 | |
| parent | 72d39062b590ce2cec391e925778a8bac23bbf88 (diff) | |
| download | riscv-isa-manual-7453397cbf24033748214a45ea6bee0bca64065a.zip riscv-isa-manual-7453397cbf24033748214a45ea6bee0bca64065a.tar.gz riscv-isa-manual-7453397cbf24033748214a45ea6bee0bca64065a.tar.bz2 | |
Add misa.F/D/Q=0 constraint
| -rw-r--r-- | src/zfinx.tex | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/zfinx.tex b/src/zfinx.tex index d5edf1d..4588f90 100644 --- a/src/zfinx.tex +++ b/src/zfinx.tex @@ -106,3 +106,11 @@ In the standard privileged architecture defined in Volume II, the {\tt mstatus} field FS is hardwired to 0 if the Zfinx extension is implemented, and FS no longer affects the trapping behavior of floating-point instructions or {\tt fcsr} accesses. + +The {\tt misa} bits F, D, and Q are hardwired to 0 when the Zfinx +extension is implemented. + +\begin{commentary} +A future discoverability mechanism might be used to probe the existence +of the Zfinx, Zhinx, Zdinx, and Zqinx extensions. +\end{commentary} |