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| author | Andrew Waterman <andrew@sifive.com> | 2021-06-08 11:00:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-08 11:00:28 -0700 |
| commit | 71a7be674f050aff5fa4460705acaa7a56f5897a (patch) | |
| tree | 33268127bcb59f73935334c6a16a62a9c75e1531 | |
| parent | f21ac49c8e37c0a3c123f04094cc22f9e476b771 (diff) | |
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PMP RWX are collectively WARL, with R=0 W=1 being illegal (#658)
| -rw-r--r-- | src/machine.tex | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex index d23a7a3..cdfc56c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3254,9 +3254,10 @@ space, so the RV64 PMP address registers impose the same limit. Figure~\ref{pmpcfg} shows the layout of a PMP configuration register. The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively. When one of these bits is clear, the -corresponding access type is denied. The combination R=0 and W=1 is reserved -for future use. The remaining two fields, A and L, are -described in the following sections. +corresponding access type is denied. +The R, W, and X fields form a collective \warl\ field for which the +combinations with R=0 and W=1 are reserved. +The remaining two fields, A and L, are described in the following sections. \begin{figure}[h!] {\footnotesize |