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authorAndrew Waterman <andrew@sifive.com>2021-10-01 17:26:17 -0700
committerAndrew Waterman <andrew@sifive.com>2021-10-01 17:26:17 -0700
commit6d363324263680bbd5e8a6ed16d2f2d42c63913f (patch)
treeca51a02f3a804e96ccf2157a13e511679bb4570f
parente511c4664368355e6d85b8e487fdfdc5d7de44e4 (diff)
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Fix permissions of *envcfg CSRs
-rw-r--r--src/priv-csrs.tex6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 99db7ce..5510452 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -199,7 +199,7 @@ Number & Privilege & Name & Description \\
\hline
\multicolumn{4}{|c|}{Supervisor Configuration} \\
\hline
-\tt 0x10A & MRW &\tt senvcfg & Supervisor environment configuration register. \\
+\tt 0x10A & SRW &\tt senvcfg & Supervisor environment configuration register. \\
\hline
\multicolumn{4}{|c|}{Supervisor Trap Handling} \\
\hline
@@ -249,8 +249,8 @@ Number & Privilege & Name & Description \\
\hline
\multicolumn{4}{|c|}{Hypervisor Configuration} \\
\hline
-\tt 0x60A & MRW &\tt henvcfg & Hypervisor environment configuration register. \\
-\tt 0x61A & MRW &\tt henvcfgh & Additional hypervisor env. conf. register, RV32 only. \\
+\tt 0x60A & HRW &\tt henvcfg & Hypervisor environment configuration register. \\
+\tt 0x61A & HRW &\tt henvcfgh & Additional hypervisor env. conf. register, RV32 only. \\
\hline
\multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\
\hline