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author | Andrew Waterman <andrew@sifive.com> | 2021-07-22 00:43:32 -0700 |
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committer | GitHub <noreply@github.com> | 2021-07-22 00:43:32 -0700 |
commit | 03ccc08a560f1a0e026eb306b2dbce4f133cc7fe (patch) | |
tree | 5d117248b50db19014f480190eae46e8de04e2fd | |
parent | 844a3df9612240a4710c04ca3c0dbd5889353493 (diff) | |
download | riscv-isa-manual-03ccc08a560f1a0e026eb306b2dbce4f133cc7fe.zip riscv-isa-manual-03ccc08a560f1a0e026eb306b2dbce4f133cc7fe.tar.gz riscv-isa-manual-03ccc08a560f1a0e026eb306b2dbce4f133cc7fe.tar.bz2 |
mstatush is not optional in priv-1.12 (#683)
But it can be hardwired to 0 in most implementations.
cc @jhauser-us
-rw-r--r-- | src/machine.tex | 3 | ||||
-rw-r--r-- | src/priv-preface.tex | 4 |
2 files changed, 2 insertions, 5 deletions
diff --git a/src/machine.tex b/src/machine.tex index b83cc62..63c0905 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -525,9 +525,6 @@ Bits 30:4 of {\tt mstatush} generally contain the same fields found in bits 62:36 of {\tt mstatus} for RV64. Fields SD, SXL, and UXL do not exist in {\tt mstatush}. -The {\tt mstatush} register is not required to be implemented if every field -would be hardwired to zero. - \begin{figure*}[h!] {\footnotesize \begin{center} diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 536d453..210e4bd 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -51,8 +51,8 @@ Additionally, the following compatible changes have been made since version \parskip 0pt \itemsep 1pt \item Removed the N extension. -\item Defined the RV32-only CSR {\tt mstatush}, which contains most of the - same fields as the upper 32 bits of RV64's {\tt mstatus}. +\item Defined the mandatory RV32-only CSR {\tt mstatush}, which contains + most of the same fields as the upper 32 bits of RV64's {\tt mstatus}. \item Permitted the unconditional delegation of less-privileged interrupts. \item Added optional big-endian and bi-endian support. \item Made priority of load/store/AMO address-misaligned exceptions |