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authorKrste Asanovic <krste@eecs.berkeley.edu>2018-08-26 16:29:25 -0700
committerKrste Asanovic <krste@eecs.berkeley.edu>2018-08-26 16:29:25 -0700
commit4cc3c1e5b4241b0fbbd36b85f54b6a02218ee421 (patch)
tree5a2592c68fc4d679c2082ad89bdffb3dcef588f9
parent9cf5c8e3eff9973bb97869419c4375fabd6e64b8 (diff)
parentd0b01fde5f10730ce898124633ac898850b31323 (diff)
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Merge branch 'master' of github.com:riscv/riscv-isa-manual
-rw-r--r--src/instr-table.tex12
-rw-r--r--src/rv32.tex4
2 files changed, 9 insertions, 7 deletions
diff --git a/src/instr-table.tex b/src/instr-table.tex
index fb312e3..bf2fb3e 100644
--- a/src/instr-table.tex
+++ b/src/instr-table.tex
@@ -433,20 +433,18 @@
\multicolumn{2}{|c|}{fm} &
\multicolumn{3}{c|}{pred} &
\multicolumn{1}{c|}{succ} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0001111} & FENCE \\
\cline{2-11}
&
-\multicolumn{2}{|c|}{0000} &
-\multicolumn{3}{c|}{0000} &
-\multicolumn{1}{c|}{0000} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{6}{|c|}{imm[11:0]} &
+\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0001111} & FENCE.I \\
\cline{2-11}
diff --git a/src/rv32.tex b/src/rv32.tex
index 9099a30..60723b6 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -1340,6 +1340,10 @@ supervisor-level operating system or debugger.
ebreak # Break to debugger
srai x0, x0, 7 # NOP encoding the semihosting call number 7
\end{verbatim}
+ Note that these three instructions must be 32-bit-wide instructions,
+ i.e., they mustn't be among the compressed 16-bit instructions
+ described in Chapter~\ref{compressed}.
+
The shift NOP instructions are still considered available for use as
HINTS.