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authorAndrew Waterman <andrew@sifive.com>2018-08-07 23:46:35 -0700
committerAndrew Waterman <andrew@sifive.com>2018-08-07 23:46:35 -0700
commit3536b679c4fcfb2cf833302d1bf960864b4c4a66 (patch)
tree0c276ceca5fb9f540ced27cdc63601e43735721d
parentce5e74a66ea22327702eca09e7a868db7e9615e9 (diff)
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Use \geq instead of >=
-rw-r--r--src/d.tex2
-rw-r--r--src/intro.tex2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/d.tex b/src/d.tex
index 080f3d6..ffd1c05 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -317,7 +317,7 @@ FSGNJ & D & src2 & src1 & J[N]/JX & dest & OP-FP \\
\end{tabular}
\end{center}
-For XLEN$>=$64 only, instructions are provided to move bit patterns
+For XLEN$\geq$64 only, instructions are provided to move bit patterns
between the floating-point and integer registers. FMV.X.D moves the
double-precision value in floating-point register {\em rs1} to a
representation in IEEE 754-2008 standard encoding in integer register
diff --git a/src/intro.tex b/src/intro.tex
index a5fd3bd..e17722a 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -459,7 +459,7 @@ word. As described in Chapter~\ref{extensions}, an implementation
that does not require support for the standard compressed instruction
extension can map 3 additional non-conforming 30-bit instruction
spaces into the 32-bit fixed-width format, while preserving support
-for standard $>=$32-bit instruction-set extensions. Further, if the
+for standard $\geq$32-bit instruction-set extensions. Further, if the
implementation also does not need instructions $>$32-bits in length,
it can recover a further four major opcodes for non-conforming extensions.
\end{samepage-commentary}