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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 12:11:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 12:13:46 -0700 |
| commit | e554c939026818337038cf2ac91d9e24d494f820 (patch) | |
| tree | 57019bf026c43b3a95a31e904bc3c4657fa46d11 | |
| parent | 645dbe107502c344c3fa3e6816cbb49fafeb8098 (diff) | |
| download | riscv-isa-manual-e554c939026818337038cf2ac91d9e24d494f820.zip riscv-isa-manual-e554c939026818337038cf2ac91d9e24d494f820.tar.gz riscv-isa-manual-e554c939026818337038cf2ac91d9e24d494f820.tar.bz2 | |
Need SFENCE after change to SBE
| -rw-r--r-- | src/machine.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 010aafc..6c79e4c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -752,6 +752,9 @@ accesses to such pages made from S-mode with {\tt sstatus}.SUM=1. For {\em implicit} accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE. +Since changing SBE alters the implementation's interpretation of these data +structures, M-mode software must follow a change to SBE by executing an +SFENCE.VMA instruction with {\em rs1}={\tt x0} and {\em rs2}={\tt x0}. If S-mode is supported, an implementation may hardwire SBE so that SBE=MBE. |