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authorAndrew Waterman <andrew@sifive.com>2019-07-18 11:28:54 -0700
committerAndrew Waterman <andrew@sifive.com>2019-07-18 12:15:35 -0700
commite31a8d67dceea32ae2a15fa52e7e43da89fe3205 (patch)
treefa9ee41b1d5efdd57a939b1c93aa1ef8b634fb72
parent18266ef5ef0400621f2545c51ca008529653440b (diff)
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Fix poor figure placement
-rw-r--r--src/machine.tex5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex
index 08240c6..6adf4f3 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2035,7 +2035,7 @@ codes.
\label{mcausereg}
\end{figure*}
-\begin{table*}[h!]
+\begin{table*}[htbp]
\begin{center}
\begin{tabular}{|r|r|l|l|}
@@ -2106,7 +2106,7 @@ decreasing priority order of Table~\ref{exception-priority}
indicates which exception is taken and reported in {\tt mcause}.
The priority of any custom synchronous exceptions is implementation-defined.
-\begin{table*}[h!]
+\begin{table*}[htbp]
\begin{center}
\begin{tabular}{|l|r|l|}
@@ -2148,6 +2148,7 @@ instruction. Therefore, these exceptions have lower priority than other
instruction address exceptions.
\end{commentary}
+\FloatBarrier
\subsection{Machine Trap Value ({\tt mtval}) Register}
The {\tt mtval} register is an MXLEN-bit read-write register formatted as shown