Clarify that CSR accesses can be ordered with FENCEs

1 files changed, 17 insertions, 0 deletions

diff --git a/src/csr.tex b/src/csr.tex
index eb7cd4a..aa0f5f8 100644
--- a/src/csr.tex
+++ b/src/csr.tex
@@ -154,3 +154,20 @@ Further assembler pseudoinstructions are defined to set and clear
 bits in the CSR when the old value is not required: CSRS/CSRC {\em
   csr, rs1}; CSRSI/CSRCI {\em csr, uimm}.
 
+
+\subsection*{CSR Access Ordering}
+
+Each RISC-V hart observes its own CSR accesses as if they were performed
+sequentially in program order.  RISC-V has a relaxed CSR ordering model
+between harts, requiring an explicit FENCE instruction to guarantee any
+specific ordering between CSR accesses and memory accesses.  For the purposes
+of the FENCE instruction (see Section~\ref{sec:fence}), CSR reads are
+considered device input (I), and CSR writes are considered device output (O).
+
+\begin{commentary}
+Some CSRs, including those defined in Chapter~\ref{sec:single-float}, are not
+accessible to other harts or devices and cause no side effects visible to
+other harts or devices when accessed locally.  Accesses to such CSRs can be
+freely reordered with respect to FENCE instructions without violating this
+specification.
+\end{commentary}