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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-24 22:58:58 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-24 22:58:58 -0700 |
| commit | cc951036c425f658ff3ff9a439eca8d995280870 (patch) | |
| tree | 638c3ae0c36aafbbf231f981e0d8d4408ff81293 | |
| parent | 6522d66574df148356a6227f6fd45f8f4a2a8ca6 (diff) | |
| download | riscv-isa-manual-cc951036c425f658ff3ff9a439eca8d995280870.zip riscv-isa-manual-cc951036c425f658ff3ff9a439eca8d995280870.tar.gz riscv-isa-manual-cc951036c425f658ff3ff9a439eca8d995280870.tar.bz2 | |
MPRV affects endianness
| -rw-r--r-- | src/hypervisor.tex | 8 | ||||
| -rw-r--r-- | src/machine.tex | 5 |
2 files changed, 7 insertions, 6 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index a224bcd..46334e1 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -193,10 +193,10 @@ For any other trap into HS-mode, STL is set to 0. The SPRV bit modifies the privilege with which loads and stores execute when not in M-mode. -When SPRV=0, translation and protection behave as normal. When SPRV=1, -load and store memory addresses are translated and protected as though -the current virtualization mode were set to {\tt hstatus}.SPV and the current -privilege mode were set to the HS-level SPP. +When SPRV=0, translation and protection behave as normal. +When SPRV=1, load and store memory addresses are translated and protected, and +endianness is applied, as though the current virtualization mode were set to +{\tt hstatus}.SPV and the current privilege mode were set to the HS-level SPP. Table~\ref{h-sprv} enumerates the cases. \begin{table*}[h!] diff --git a/src/machine.tex b/src/machine.tex index 2c8f6e7..3a6b54a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -681,8 +681,9 @@ widest supported width not wider than the new MXLEN. The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute in all privilege modes. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the -current privilege mode. When MPRV=1, load and store memory addresses are -translated and protected as though the current privilege mode were set to MPP. +current privilege mode. +When MPRV=1, load and store memory addresses are translated and protected, and +endianness is applied, as though the current privilege mode were set to MPP. Instruction address-translation and protection are unaffected by the setting of MPRV. MPRV is hardwired to 0 if U-mode is not supported. |