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| author | Philipp Wagner <phw@lowrisc.org> | 2019-05-31 10:00:27 +0100 |
|---|---|---|
| committer | Philipp Wagner <phw@lowrisc.org> | 2019-05-31 10:00:27 +0100 |
| commit | bed1abee2e3acd2fd2fac3b5ecce7fc813e8b16f (patch) | |
| tree | 6a664c3300982648a5ed00f8fa3ccb16d00acc5b | |
| parent | 21c6a1412e1822fd906c0de9b841b90a060069e1 (diff) | |
| download | riscv-isa-manual-bed1abee2e3acd2fd2fac3b5ecce7fc813e8b16f.zip riscv-isa-manual-bed1abee2e3acd2fd2fac3b5ecce7fc813e8b16f.tar.gz riscv-isa-manual-bed1abee2e3acd2fd2fac3b5ecce7fc813e8b16f.tar.bz2 | |
Tiny editorial fix
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 18aeedf..3f3d956 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1694,7 +1694,7 @@ corresponding bit is set in {\tt scounteren}, then U-mode is also permitted to access that register. Registers {\tt mcounteren} and {\tt scounteren} are \warl\ registers -that must be implemented if U-mode and S-mode are implemented, +that must be implemented if U-mode and S-mode are implemented. Any of the bits may contain a hardwired value of zero, indicating reads to the corresponding counter will cause an illegal instruction exception when executing in a less-privileged mode. |