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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-25 16:58:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-25 16:58:30 -0700 |
| commit | 65dda61954ba02534758c97868fe28fbdca018c1 (patch) | |
| tree | 6a5cacf00ea54f445c4661e77a5b9a7f20b98fae | |
| parent | cc951036c425f658ff3ff9a439eca8d995280870 (diff) | |
| download | riscv-isa-manual-65dda61954ba02534758c97868fe28fbdca018c1.zip riscv-isa-manual-65dda61954ba02534758c97868fe28fbdca018c1.tar.gz riscv-isa-manual-65dda61954ba02534758c97868fe28fbdca018c1.tar.bz2 | |
ECALL and EBREAK don't retire
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 3a6b54a..d723911 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2296,6 +2296,8 @@ as the EBREAK instruction. ECALL and EBREAK cause the receiving privilege mode's {\tt epc} register to be set to the address of the ECALL or EBREAK instruction itself, {\em not} the address of the following instruction. +As ECALL and EBREAK cause synchronous exceptions, they are not considered to +retire, and should not increment the {\tt minstret} CSR. \subsection{Trap-Return Instructions} \label{otherpriv} |