Merge pull request #395 from riscv/endianness

Add endianness control proposal to priv spec

4 files changed, 215 insertions, 38 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 3f3d956..6c79e4c 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1,4 +1,4 @@
-\chapter{Machine-Level ISA, Version 1.11}
+\chapter{Machine-Level ISA, Version 1.12}
 \label{machine}
 
 This chapter describes the machine-level operations available in
@@ -355,11 +355,11 @@ For efficiency, system implementers should aim to reduce the magnitude
 of the largest hart ID used in a system.
 \end{commentary}
 
-\subsection{Machine Status Register ({\tt mstatus})}
+\subsection{Machine Status Registers ({\tt mstatus} and {\tt mstatush})}
 
 The {\tt mstatus} register is an MXLEN-bit read/write register
-formatted as shown in Figure~\ref{mstatusreg-rv32} for RV32 and
-Figure~\ref{mstatusreg} for RV64.  The {\tt mstatus}
+formatted as shown in Figure~\ref{mstatusreg} for RV64 and
+Figure~\ref{mstatusreg-rv32} for RV32.  The {\tt mstatus}
 register keeps track of and controls the hart's current operating
 state.  Restricted views of the {\tt mstatus} register appear as the
 {\tt sstatus} and {\tt ustatus} registers in the S-level and U-level
@@ -369,33 +369,42 @@ ISAs respectively.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{cKccccccc}
+\begin{tabular}{cRccccYcccccc}
 \\
-\instbit{31} &
-\instbitrange{30}{23} &
+\instbit{MXLEN-1} &
+\instbitrange{MXLEN-2}{38} &
+\instbit{37} &
+\instbit{36} &
+\instbitrange{35}{34} &
+\instbitrange{33}{32} &
+\instbitrange{31}{23} &
 \instbit{22} &
 \instbit{21} &
 \instbit{20} &
 \instbit{19} &
 \instbit{18} &
-\instbit{17} &
  \\
 \hline
 \multicolumn{1}{|c|}{SD} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{MBE} &
+\multicolumn{1}{c|}{SBE} &
+\multicolumn{1}{c|}{SXL[1:0]} &
+\multicolumn{1}{c|}{UXL[1:0]} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{TSR} &
 \multicolumn{1}{c|}{TW} &
 \multicolumn{1}{c|}{TVM} &
 \multicolumn{1}{c|}{MXR} &
 \multicolumn{1}{c|}{SUM} &
-\multicolumn{1}{c|}{MPRV} &
  \\
 \hline
-1 & 8 & 1 & 1 & 1 & 1 & 1 & 1 & \\
+1 & MXLEN-39 & 1 & 1 & 2 & 2 & 9 & 1 & 1 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cccccccccccccc}
+\begin{tabular}{ccccccccccccccc}
 \\
 &
+\instbit{17} &
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
 \instbitrange{12}{11} &
@@ -411,13 +420,14 @@ ISAs respectively.
 \instbit{0} \\
 \hline
  &
-\multicolumn{1}{|c|}{XS[1:0]} &
+\multicolumn{1}{|c|}{MPRV} &
+\multicolumn{1}{c|}{XS[1:0]} &
 \multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{MPP[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{MPIE} &
-\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{MIE} &
@@ -425,26 +435,23 @@ ISAs respectively.
 \multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{UIE} \\
 \hline
- & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
+ & 1 & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
 \vspace{-0.1in}
-\caption{Machine-mode status register ({\tt mstatus}) for RV32.}
-\label{mstatusreg-rv32}
+\caption{Machine-mode status register ({\tt mstatus}) for RV64.}
+\label{mstatusreg}
 \end{figure*}
 
 \begin{figure*}[h!]
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{cRccYccccccc}
+\begin{tabular}{cKccccccc}
 \\
-\instbit{MXLEN-1} &
-\instbitrange{MXLEN-2}{36} &
-\instbitrange{35}{34} &
-\instbitrange{33}{32} &
-\instbitrange{31}{23} &
+\instbit{31} &
+\instbitrange{30}{23} &
 \instbit{22} &
 \instbit{21} &
 \instbit{20} &
@@ -455,9 +462,6 @@ ISAs respectively.
 \hline
 \multicolumn{1}{|c|}{SD} &
 \multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{SXL[1:0]} &
-\multicolumn{1}{c|}{UXL[1:0]} &
-\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{TSR} &
 \multicolumn{1}{c|}{TW} &
 \multicolumn{1}{c|}{TVM} &
@@ -466,7 +470,7 @@ ISAs respectively.
 \multicolumn{1}{c|}{MPRV} &
  \\
 \hline
-1 & MXLEN-37 & 2 & 2 & 9 & 1 & 1 & 1 & 1 & 1 & 1 & \\
+1 & 8 & 1 & 1 & 1 & 1 & 1 & 1 & \\
 \end{tabular}
 \begin{tabular}{cccccccccccccc}
 \\
@@ -492,7 +496,7 @@ ISAs respectively.
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{MPIE} &
-\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{MIE} &
@@ -505,8 +509,42 @@ ISAs respectively.
 \end{center}
 }
 \vspace{-0.1in}
-\caption{Machine-mode status register ({\tt mstatus}) for RV64.}
-\label{mstatusreg}
+\caption{Machine-mode status register ({\tt mstatus}) for RV32.}
+\label{mstatusreg-rv32}
+\end{figure*}
+
+For RV32 only, {\tt mstatush} is a 32-bit read/write register formatted
+as shown in Figure~\ref{mstatushreg}.
+Bits 30:4 of {\tt mstatush} generally contain the same fields found in
+bits 62:36 of {\tt mstatus} for RV64.
+Fields SD, SXL, and UXL do not exist in {\tt mstatush}.
+
+The {\tt mstatush} register is not required to be implemented if every field
+would be hardwired to zero.
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{JccF}
+\\
+\instbitrange{31}{6} &
+\instbit{5} &
+\instbit{4} &
+\instbitrange{3}{0} \\
+\hline
+\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{c|}{MBE} &
+\multicolumn{1}{c|}{SBE} &
+\multicolumn{1}{c|}{\wpri} \\
+\hline
+26 & 1 & 1 & 4 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Additional machine-mode status register ({\tt mstatush}) for RV32.}
+\label{mstatushreg}
 \end{figure*}
 
 
@@ -684,6 +722,98 @@ encoded in page-table entries.  In particular, they have no impact on whether
 access exceptions are raised due to PMAs or PMP.
 \end{commentary}
 
+\subsubsection{Endianness Control in {\tt mstatus} and {\tt mstatush} Registers}
+
+The MBE, SBE, and UBE bits in {\tt mstatus} and {\tt mstatush} are
+\warl\ fields that control the endianness of memory accesses other than
+instruction fetches.
+Instruction fetches are always little-endian.
+
+MBE controls whether non-instruction-fetch memory accesses made from
+M-mode (assuming {\tt mstatus}.MPRV=0) are little-endian (MBE=0) or
+big-endian (MBE=1).
+
+If S-mode is not supported, SBE is hardwired to~0.
+Otherwise, when address translation is not active, SBE controls whether
+explicit load and store memory accesses made from S-mode are
+little-endian (SBE=0) or big-endian (SBE=1).
+When page-based address translation is active, SBE controls whether
+explicit memory accesses to non-U-mode-accessible pages (U=0 in
+Figure~\ref{sv32pte}) are little-endian or big-endian.
+
+If U-mode is not supported, UBE is hardwired to~0.
+Otherwise, when address translation is not active, UBE controls whether
+explicit load and store memory accesses made from U-mode are
+little-endian (UBE=0) or big-endian (UBE=1).
+When page-based address translation is active, UBE controls whether
+explicit memory accesses to U-mode-accessible pages (U=1 in
+Figure~\ref{sv32pte}) are little-endian or big-endian, including explicit
+accesses to such pages made from S-mode with {\tt sstatus}.SUM=1.
+
+For {\em implicit} accesses to supervisor-level memory management data
+structures, such as page tables, endianness is always controlled by SBE.
+Since changing SBE alters the implementation's interpretation of these data
+structures, M-mode software must follow a change to SBE by executing an
+SFENCE.VMA instruction with {\em rs1}={\tt x0} and {\em rs2}={\tt x0}.
+
+If S-mode is supported, an implementation may hardwire SBE so that
+SBE=MBE.
+If U-mode is supported, an implementation may hardwire UBE so that
+UBE=MBE or UBE=SBE.
+
+\begin{commentary}
+An implementation supports only little-endian memory accesses if fields
+MBE, SBE, and UBE are all hardwired to~0.
+An implementation supports only big-endian memory accesses (aside from
+instruction fetches) if MBE is hardwired to 1 and SBE and UBE are each
+hardwired to 1 when S-mode and U-mode are supported.
+\end{commentary}
+
+\begin{commentary}
+Volume I defines a hart's address space as a circular sequence of
+$2^{XLEN}$ bytes at consecutive addresses.
+The correspondence between addresses and byte locations is fixed and not
+affected by any endianness mode.
+Rather, the applicable endianness mode determines the order of mapping
+between memory bytes and a multibyte quantity (halfword, word, etc.).
+\end{commentary}
+
+\begin{commentary}
+Standard RISC-V ABIs are expected to be purely little-endian-only or
+big-endian-only, with no accommodation for mixing endianness.
+Nevertheless, endianness control has been defined so as to permit, for
+instance, an OS of one endianness to execute user-mode programs of the
+opposite endianness.
+Consideration has been given also to the possibility of nonstandard
+usages whereby software flips the endianness of memory accesses as
+needed.
+
+When page-based address translation is active, pages that are accessible
+to user mode have endianness determined by UBE, even if the access is
+made from S-mode (with {\tt sstatus}.SUM=1).
+Pages that are not accessible to user mode have endianness determined by
+SBE.
+\end{commentary}
+
+\begin{commentary}
+RISC-V instructions are uniformly little-endian to decouple instruction
+encoding from the current endianness settings, for the benefit of both
+hardware and software.
+Otherwise, for instance, a RISC-V assembler or disassembler would always
+need to know the intended active endianness, despite that the endianness
+mode might change dynamically during execution.
+In contrast, by giving instructions a fixed endianness, it is sometimes
+possible for carefully written software to be endianness-agnostic even in
+binary form, much like position-independent code.
+
+The choice to have instructions be only little-endian does have
+consequences, however, for RISC-V software that encodes or decodes
+machine instructions.
+In big-endian mode, such software must account for the fact that explicit
+loads and stores have endianness opposite that of instructions, for
+example by swapping byte order after loads and before stores.
+\end{commentary}
+
 \subsubsection{Virtualization Support in {\tt mstatus} Register}
 \label{virt-control}
 
@@ -2331,6 +2461,8 @@ arrival.
 
 Upon reset, a hart's privilege mode is set to M.  The {\tt mstatus} fields MIE
 and MPRV are reset to 0.
+If little-endian memory accesses are supported, the {\tt mstatus}/{\tt mstatush}
+field MBE is reset to 0.
 The {\tt misa} register is reset to enable the maximal set of supported
 extensions and widest MXLEN, as described in Section~\ref{sec:misa}.
 The {\tt pc} is set to an implementation-defined
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 445a2b7..dad890b 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -281,6 +281,7 @@ Number    & Privilege & Name & Description \\
 \tt 0x304 & MRW  &\tt mie        & Machine interrupt-enable register. \\
 \tt 0x305 & MRW  &\tt mtvec      & Machine trap-handler base address. \\
 \tt 0x306 & MRW  &\tt mcounteren & Machine counter enable. \\
+\tt 0x310 & MRW  &\tt mstatush   & Additional machine status register, RV32 only. \\
 \hline
 \multicolumn{4}{|c|}{Machine Trap Handling} \\
 \hline
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 1ed7b39..660a412 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -29,8 +29,11 @@ Changes from version 1.11 include:
 \begin{itemize}
   \parskip 0pt
   \itemsep 1pt
+\item Defined the RV32-only CSR {\tt mstatush}, which contains most of the
+  same fields as the upper 32 bits of RV64's {\tt mstatus}.
 \item A revised hypervisor architecture proposal that represents VS-mode
   CSR state more simply.
+\item Added optional big-endian and bi-endian support.
 \end{itemize}
 
 \newpage
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 503c8bd..29afbca 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1,4 +1,4 @@
-\chapter{Supervisor-Level ISA, Version 1.11}
+\chapter{Supervisor-Level ISA, Version 1.12}
 \label{supervisor}
 
 This chapter describes the RISC-V supervisor-level architecture, which
@@ -12,7 +12,7 @@ interrupts, to support clean virtualization.
 In this spirit, certain supervisor-level facilities, including requests for
 timer and interprocessor interrupts, are provided by implementation-specific
 mechanisms.  In some systems, a supervisor execution environment (SEE)
-provides these facilities in a manner specified by a superivsor binary
+provides these facilities in a manner specified by a supervisor binary
 interface (SBI).  Other systems supply these facilities directly, through some
 other implementation-defined mechanism.
 \end{commentary}
@@ -46,7 +46,8 @@ register keeps track of the processor's current operating state.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\begin{tabular}{cWcccccWcWccWcc}
+\scalebox{0.95}{
+\begin{tabular}{cWcccccWcccccWcc}
 \\
 \instbit{31} &
 \instbitrange{30}{20} &
@@ -57,7 +58,8 @@ register keeps track of the processor's current operating state.
 \instbitrange{14}{13} &
 \instbitrange{12}{9} &
 \instbit{8} &
-\instbitrange{7}{6} &
+\instbit{7} &
+\instbit{6} &
 \instbit{5} &
 \instbit{4} &
 \instbitrange{3}{2} &
@@ -74,6 +76,7 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
@@ -81,8 +84,8 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{c|}{UIE}
 \\
 \hline
-1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
-\end{tabular}
+1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
+\end{tabular}}
 \end{center}
 }
 \vspace{-0.1in}
@@ -116,14 +119,15 @@ register keeps track of the processor's current operating state.
 \hline
 1 & SXLEN-35 & 2 & 12 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{ccccccccccc}
+\begin{tabular}{cccccccccccc}
 \\
 &
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
 \instbitrange{12}{9} &
 \instbit{8} &
-\instbitrange{7}{6} &
+\instbit{7} &
+\instbit{6} &
 \instbit{5} &
 \instbit{4} &
 \instbitrange{3}{2} &
@@ -136,13 +140,14 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{UPIE} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{UIE} \\
 \hline
- & 2 & 2 & 4 & 1 & 2 & 1 & 1 & 2 & 1 & 1 \\
+ & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 1 & 2 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
@@ -242,6 +247,42 @@ instruction page-fault handler to direct supervisor software to use the
 alternate mapping.
 \end{commentary}
 
+\subsection{Endianness Control in {\tt sstatus} Register}
+
+The UBE bit is a \warl\ field that controls the endianness of explicit
+memory accesses for U-mode, which may differ from the endianness of
+memory accesses in S-mode.
+An implementation may hardwire UBE to specify always the same endianness
+as for S-mode.
+
+UBE has no effect on instruction fetches, which are {\em implicit} memory
+accesses that are always little-endian.
+
+When address translation is not active, UBE controls whether explicit
+load and store memory accesses made from U-mode are little-endian (UBE=0)
+or big-endian (UBE=1).
+When page-based address translation is active, UBE controls whether
+explicit memory accesses to U-mode-accessible pages (U=1 in
+Figure~\ref{sv32pte}) are little-endian or big-endian, including explicit
+accesses to such pages made from S-mode with SUM=1.
+
+For {\em implicit} accesses to supervisor-level memory management data
+structures, such as page tables, S-mode endianness always applies and UBE
+is ignored.
+
+\begin{commentary}
+Standard RISC-V ABIs are expected to be purely little-endian-only or
+big-endian-only, with no accommodation for mixing endianness.
+Nevertheless, endianness control has been defined so as to permit an
+OS of one endianness to execute user-mode programs of the opposite
+endianness.
+
+When page-based address translation is active, pages that are accessible
+to user mode have endianness determined by UBE, even if the access is
+made from S-mode (with SUM=1).
+For pages that are not accessible to user mode, UBE is ignored.
+\end{commentary}
+
 \subsection{Supervisor Trap Vector Base Address Register ({\tt stvec})}
 
 The {\tt stvec} register is an SXLEN-bit read/write register that holds