Merge branch 'master' into counterinhibit-smt

5 files changed, 26 insertions, 42 deletions

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index a224bcd..46334e1 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -193,10 +193,10 @@ For any other trap into HS-mode, STL is set to 0.
 
 The SPRV bit modifies the privilege with which loads and stores execute when
 not in M-mode.
-When SPRV=0, translation and protection behave as normal.  When SPRV=1,
-load and store memory addresses are translated and protected as though
-the current virtualization mode were set to {\tt hstatus}.SPV and the current
-privilege mode were set to the HS-level SPP.
+When SPRV=0, translation and protection behave as normal.
+When SPRV=1, load and store memory addresses are translated and protected, and
+endianness is applied, as though the current virtualization mode were set to
+{\tt hstatus}.SPV and the current privilege mode were set to the HS-level SPP.
 Table~\ref{h-sprv} enumerates the cases.
 
 \begin{table*}[h!]
diff --git a/src/machine.tex b/src/machine.tex
index 9416df9..cde159e 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -681,8 +681,9 @@ widest supported width not wider than the new MXLEN.
 The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads
 and stores execute in all privilege modes.  When MPRV=0, loads and stores
 behave as normal, using the translation and protection mechanisms of the
-current privilege mode.  When MPRV=1, load and store memory addresses are
-translated and protected as though the current privilege mode were set to MPP.
+current privilege mode.
+When MPRV=1, load and store memory addresses are translated and protected, and
+endianness is applied, as though the current privilege mode were set to MPP.
 Instruction address-translation and protection are unaffected by the setting
 of MPRV.  MPRV is hardwired to 0 if U-mode is not supported.
 
@@ -736,21 +737,12 @@ M-mode (assuming {\tt mstatus}.MPRV=0) are little-endian (MBE=0) or
 big-endian (MBE=1).
 
 If S-mode is not supported, SBE is hardwired to~0.
-Otherwise, when address translation is not active, SBE controls whether
-explicit load and store memory accesses made from S-mode are
-little-endian (SBE=0) or big-endian (SBE=1).
-When page-based address translation is active, SBE controls whether
-explicit memory accesses to non-U-mode-accessible pages (U=0 in
-Figure~\ref{sv32pte}) are little-endian or big-endian.
+Otherwise, SBE controls whether explicit load and store memory accesses made
+from S-mode are little-endian (SBE=0) or big-endian (SBE=1).
 
 If U-mode is not supported, UBE is hardwired to~0.
-Otherwise, when address translation is not active, UBE controls whether
-explicit load and store memory accesses made from U-mode are
-little-endian (UBE=0) or big-endian (UBE=1).
-When page-based address translation is active, UBE controls whether
-explicit memory accesses to U-mode-accessible pages (U=1 in
-Figure~\ref{sv32pte}) are little-endian or big-endian, including explicit
-accesses to such pages made from S-mode with {\tt sstatus}.SUM=1.
+Otherwise, UBE controls whether explicit load and store memory accesses made
+from U-mode are little-endian (UBE=0) or big-endian (UBE=1).
 
 For {\em implicit} accesses to supervisor-level memory management data
 structures, such as page tables, endianness is always controlled by SBE.
@@ -800,12 +792,6 @@ opposite endianness.
 Consideration has been given also to the possibility of nonstandard
 usages whereby software flips the endianness of memory accesses as
 needed.
-
-When page-based address translation is active, pages that are accessible
-to user mode have endianness determined by UBE, even if the access is
-made from S-mode (with {\tt sstatus}.SUM=1).
-Pages that are not accessible to user mode have endianness determined by
-SBE.
 \end{commentary}
 
 \begin{commentary}
@@ -2314,6 +2300,8 @@ as the EBREAK instruction.
 ECALL and EBREAK cause the receiving privilege mode's {\tt epc} register
 to be set to the address of the ECALL or EBREAK instruction itself, {\em not}
 the address of the following instruction.
+As ECALL and EBREAK cause synchronous exceptions, they are not considered to
+retire, and should not increment the {\tt minstret} CSR.
 
 \subsection{Trap-Return Instructions}
 \label{otherpriv}
@@ -3272,6 +3260,11 @@ If no PMP entry matches an M-mode access, the access succeeds.  If no PMP
 entry matches an S-mode or U-mode access, but at least one PMP entry is
 implemented, the access fails.
 
+\begin{commentary}
+If at least one PMP entry is implemented, but all PMP entries' A fields are
+set to OFF, then all S-mode and U-mode memory accesses will fail.
+\end{commentary}
+
 Failed accesses generate a load, store, or instruction access exception.  Note
 that a single instruction may generate multiple accesses, which may not be
 mutually atomic.  An access exception is generated if at least one access
diff --git a/src/preface.tex b/src/preface.tex
index 86ecf84..0d3dd66 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -167,9 +167,9 @@ The changes in this version of the document include:
 \item Improvements to the description and commentary.
 \item Defined the term IALIGN as shorthand to describe the instruction-address
   alignment constraint.
-\item Removed text of P extension chapter as now superceded by active task
+\item Removed text of P extension chapter as now superseded by active task
   group documents.
-\item Removed text of V extension chapter as now superceded by separate vector
+\item Removed text of V extension chapter as now superseded by separate vector
   extension draft document.
 \end{itemize}
 
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
index d55b4a1..1b0bb0a 100644
--- a/src/riscv-privileged.tex
+++ b/src/riscv-privileged.tex
@@ -35,7 +35,7 @@
 
 Contributors to all versions of the spec in alphabetical order (please contact
 editors to suggest corrections): Krste Asanovi\'{c}, Peter Ashenden, Rimas
-Avi\v{z}ienis, Jacob Bachmeyer, Allen J. Baum, Paolo Bonzini, Ruslan Bukin,
+Avi\v{z}ienis, Jacob Bachmeyer, Allen J. Baum, Jonathan Behrens, Paolo Bonzini, Ruslan Bukin,
 Christopher Celio, Chuanhua Chang, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte
 Dalrymple, Dennis Ferguson,  Marc Gauthier,
 Gary Guo, Mike Frysinger, John Hauser, David Horner, Olof
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 29afbca..4173456 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -250,21 +250,17 @@ alternate mapping.
 \subsection{Endianness Control in {\tt sstatus} Register}
 
 The UBE bit is a \warl\ field that controls the endianness of explicit
-memory accesses for U-mode, which may differ from the endianness of
+memory accesses made from U-mode, which may differ from the endianness of
 memory accesses in S-mode.
 An implementation may hardwire UBE to specify always the same endianness
 as for S-mode.
 
-UBE has no effect on instruction fetches, which are {\em implicit} memory
-accesses that are always little-endian.
-
-When address translation is not active, UBE controls whether explicit
+UBE controls whether explicit
 load and store memory accesses made from U-mode are little-endian (UBE=0)
 or big-endian (UBE=1).
-When page-based address translation is active, UBE controls whether
-explicit memory accesses to U-mode-accessible pages (U=1 in
-Figure~\ref{sv32pte}) are little-endian or big-endian, including explicit
-accesses to such pages made from S-mode with SUM=1.
+
+UBE has no effect on instruction fetches, which are {\em implicit} memory
+accesses that are always little-endian.
 
 For {\em implicit} accesses to supervisor-level memory management data
 structures, such as page tables, S-mode endianness always applies and UBE
@@ -276,11 +272,6 @@ big-endian-only, with no accommodation for mixing endianness.
 Nevertheless, endianness control has been defined so as to permit an
 OS of one endianness to execute user-mode programs of the opposite
 endianness.
-
-When page-based address translation is active, pages that are accessible
-to user mode have endianness determined by UBE, even if the access is
-made from S-mode (with SUM=1).
-For pages that are not accessible to user mode, UBE is ignored.
 \end{commentary}
 
 \subsection{Supervisor Trap Vector Base Address Register ({\tt stvec})}