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| author | Andrew Waterman <andrew@sifive.com> | 2017-06-14 14:46:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-06-14 14:47:09 -0700 |
| commit | 8e3f8a50f2a31cc9c0a8ea901a1e6773358c6e38 (patch) | |
| tree | 0a970efc230a474d4383ab7999f28b77627bb6ae | |
| parent | 227cd5bc6628026f34a257207c5ab4ea734e8d07 (diff) | |
| download | riscv-isa-manual-8e3f8a50f2a31cc9c0a8ea901a1e6773358c6e38.zip riscv-isa-manual-8e3f8a50f2a31cc9c0a8ea901a1e6773358c6e38.tar.gz riscv-isa-manual-8e3f8a50f2a31cc9c0a8ea901a1e6773358c6e38.tar.bz2 | |
Remove FSFLAGSI, FSRMI pseudoinstructions
They have never implemented and are too uncommon to justify
pseudoinstructions instead of using CSRWI/CSRRWI directly.
| -rw-r--r-- | src/assembly.tex | 4 | ||||
| -rw-r--r-- | src/f.tex | 4 |
2 files changed, 1 insertions, 7 deletions
diff --git a/src/assembly.tex b/src/assembly.tex index d58f33d..04165f3 100644 --- a/src/assembly.tex +++ b/src/assembly.tex @@ -138,14 +138,10 @@ Pseudoinstruction & Base Instruction & Meaning \\ \hline {\tt frrm rd} & {\tt csrrs rd, frm, x0} & Read FP rounding mode \\ {\tt fsrm rd, rs} & {\tt csrrw rd, frm, rs} & Swap FP rounding mode \\ {\tt fsrm rs} & {\tt csrrw x0, frm, rs} & Write FP rounding mode \\ -{\tt fsrmi rd, imm} & {\tt csrrwi rd, frm, imm} & Swap FP rounding mode, immediate \\ -{\tt fsrmi imm} & {\tt csrrwi x0, frm, imm} & Write FP rounding mode, immediate \\ \hline {\tt frflags rd} & {\tt csrrs rd, fflags, x0} & Read FP exception flags \\ {\tt fsflags rd, rs} & {\tt csrrw rd, fflags, rs} & Swap FP exception flags \\ {\tt fsflags rs} & {\tt csrrw x0, fflags, rs} & Write FP exception flags \\ -{\tt fsflagsi rd, imm} & {\tt csrrwi rd, fflags, imm} & Swap FP exception flags, immediate \\ -{\tt fsflagsi imm} & {\tt csrrwi x0, fflags, imm} & Write FP exception flags, immediate \\ \hline \end{tabular} @@ -144,9 +144,7 @@ swaps the value in {\tt frm} by copying the original value into integer register {\em rd}, and then writing a new value obtained from the three least-significant bits of integer register {\em rs1} into {\tt frm}. FRFLAGS and FSFLAGS are defined analogously for the -Accrued Exception Flags field {\tt fflags}. Additional -pseudo-instructions FSRMI and FSFLAGSI swap values using an immediate -value instead of register {\em rs1}. +Accrued Exception Flags field {\tt fflags}. Bits 31--8 of the {\tt fcsr} are reserved for other standard extensions, including the ``L'' standard extension for decimal floating-point. If |