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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-12 01:01:33 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-12 01:01:33 -0800 |
| commit | 1b74dd69a400a1e9244e9a9f48174d38ec1b3a7e (patch) | |
| tree | acf30aac72123fc3d7aa6d13cf57e235828d7bc0 | |
| parent | 9c5a2d47f029b1982410658c421b9866d251ca52 (diff) | |
| download | riscv-isa-manual-1b74dd69a400a1e9244e9a9f48174d38ec1b3a7e.zip riscv-isa-manual-1b74dd69a400a1e9244e9a9f48174d38ec1b3a7e.tar.gz riscv-isa-manual-1b74dd69a400a1e9244e9a9f48174d38ec1b3a7e.tar.bz2 | |
Clarify WLRL semantics
| -rw-r--r-- | src/priv-csrs.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index c027bc2..e13e96a 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -416,7 +416,7 @@ instruction exception if an instruction attempts to write a non-supported value to a CSR field. Hardware implementations can return arbitrary bit patterns on the read of a CSR field when the last write was of an illegal value, but the value returned should -deterministically depend on the previous written value. +deterministically depend on the illegal written value. \subsection*{Write Any Values, Reads Legal Values (WARL)} |