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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-06-08 07:35:06 -0400 |
|---|---|---|
| committer | Daniel Lustig <dlustig@nvidia.com> | 2021-06-08 07:35:06 -0400 |
| commit | 031f1922ac2caccfd4a1897d48cdc4728c46833f (patch) | |
| tree | 1af80c2ad998d75a492fd361da131ac4543cc072 | |
| parent | e2f81a1791cf5f0483200c3c37150d0f2eccc485 (diff) | |
| parent | 4e766853862e5ad370c51dfe45b49f15b2439ca5 (diff) | |
| download | riscv-isa-manual-031f1922ac2caccfd4a1897d48cdc4728c46833f.zip riscv-isa-manual-031f1922ac2caccfd4a1897d48cdc4728c46833f.tar.gz riscv-isa-manual-031f1922ac2caccfd4a1897d48cdc4728c46833f.tar.bz2 | |
Merge branch 'virtual-memory' into Svnapot
| -rw-r--r-- | src/priv-preface.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 0ca835c..c4e5383 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -45,8 +45,9 @@ portability problems in practice: \item PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. \item Allowed for speculative updates of page table entry A bits. -\item Clarify that PTEs with reserved bits set should trigger page-fault - exceptions. +\item Clarify that PTEs with reserved bits set and non-leaf PTEs with D, A, + or U set should trigger page-fault exceptions when accessed by the + address-translation algorithm. \end{itemize} Additionally, the following compatible changes have been made since version |