From 4e766853862e5ad370c51dfe45b49f15b2439ca5 Mon Sep 17 00:00:00 2001 From: Daniel Lustig Date: Tue, 8 Jun 2021 07:30:48 -0400 Subject: Non-leaf PTEs with D/A/U set trigger a page fault See #651 --- src/priv-preface.tex | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/priv-preface.tex b/src/priv-preface.tex index c25c4f7..a77b738 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -44,8 +44,9 @@ portability problems in practice: \item PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. \item Allowed for speculative updates of page table entry A bits. -\item Clarify that PTEs with reserved bits set should trigger page-fault - exceptions. +\item Clarify that PTEs with reserved bits set and non-leaf PTEs with D, A, + or U set should trigger page-fault exceptions when accessed by the + address-translation algorithm. \end{itemize} Additionally, the following compatible changes have been made since version -- cgit v1.1